lecture asip 8, 9

7/28/2019 Lecture ASIP 8, 9

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VLSI Architecture :: MEL G642

MEL G642

Dr. A. Amalin PrinceBITS Pilani K.K. Birla Goa Campus

Department of Electrical , Electronics and Instrumentation Engineering



Contents

MAC fundamentalsMAC implementations

A MAC case studyMAC integration

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Datapath in a DSP processor

RF ALU

The data path (DP)

h ( C P )

MAC

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PM

DM1 DM2

AGU2

Addressing path (AGU)

AGU1

C o n

t r o

l p a

rocessor memory an reg ster usses



MAC general

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MAC instructions

Multiplication arithmetic'sMAC & Iterative instructions

Double-precision arithmetic instructionsMove data from and to MAC

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Other instructions



Why MAC

MAC: Multiplication and accumulation unit– Performs convolution based algorithms

o

FIR, IIR, Auto correlation, Cross correlation– Support most transformation algorithms

o FFT and DCT need MAC hardware

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x n

c(0)

Z-1

c(1)

x(n-1)

+

Z-1

c(2)

x(n-2)

+

Z-1

c(3)

x(n-3)

+

Z-1

c(4)

x(n-4)

+y(n)



Why MAC

Data x(n) is shifted through a FIFO buffer consisting of 4registersSo that x(n) become x(n-1) and x(n-1) become x(n-2) …the next clock cycle

∑−

=

−=

1

0

)()()(m

i

icin xn y

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All arithmetic executions are mapped to hardware inparallelThere are four multipliers and four full adders

A sample of y(n) is computed per clock cycle y(n) = x(n)*c(0) + x(n-1)*c(1) + x(n-2)*c(2 )+ x(n-3)*c(3 )+ x(n-4)*c(4)



MAC basics

MAC: Multiplication and accumulation unit– Adder = accumulator; Accumulator register

MOA MOB

Multiplier

MOA MOB

Multiplier

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AccumulatorACR

AOA AOB

ACR =Accumulating

registerFlag circuit

AccumulatorACR

AOA AOB

ACR =Accumulating

registerFlag circuit

pe ne

(a) MAC without pipeline (b) MAC with pipeline



MUL circuit

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Multiplications

How to manage double precision?How to manage signed?

Hardware multiplication

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Fractional multiplication Integer multiplication

Signed multiplication Unsigned multiplication

Result with

double precision

Result with

single precisoin



Multiplications

How to manage double precision?How to manage signed?

Hardware multiplication

The 16-bit signed and 16-bit unsigned multiplicationcan be implemented based

on a 17b × 17b signedmultiplier.In general, a (N+1)×(N+1)

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Fractional multiplication Integer multiplication

Signed multiplication Unsigned multiplication

Result with

double precision

Result with

single precisoin

can give N bits signed and unsigned multiplication



Basic multiplication instructions

No. Specifications on the result

M1 Signed integer multiplication, double precision resultACR [31:0] <= {A[15], A[15:0]} * {B[15], B[15:0]}

M2 Signed-Unsigned integer multiplication, double precision resultACR [31:0] <= {A[15], A[15:0]} * { “0” , B[15:0]}

M3 Unsigned-signed integer multiplication, double precision result= “ ” *

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, ,

M4 Unsigned-Unsigned integer multiplication, double precision resultACR [31:0] <= { “0”, A[15:0]} * { “0” , B[15:0]}

M5 Signed integer multiplication, single precision result no roundACR [31:16] <= SAT(2 16*({A[15], A[15:0]} * {B[15], B[15:0]}))

M6 Signed fractional multiplication, double precision resultACR [31:0] <= SAT (2*({A[15], A[15:0]} * {B[15], B[15:0]}))

M7 Signed fractional multiplication, single precision rounded result

ACR [31:16] <= SAT(Round(2*({A[15], A[15:0]} * {B[15], B[15:0]})))



Multiplication of long data

ACR [47:0] <= {X[31], X[31:16]} * {Y[15], Y[15:0]}

+ 2-16

*( “0”, X[15:0]} * {Y[15], Y[15:0]});

ACR <=X[31:0]× Y[15:0]

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ACR [64:0] <= {X[31], X[31:16]} * {Y[31], Y[31:16]}+ 2 -16*({ “0”, X[15:0]} * {Y[31], Y[31:16]})+ 2 -16*({X[31], X[31:16]} * {“0”, Y[15:0]})

+ 2 -32*({“0”, X[15:0]} * {“0”, Y[15:0]});

ACR<= X[31:0] ×Y[31:0]



An example of MUL

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MAC instructions

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Guard Operations In MAC

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G 6 4 2

i r c u i t

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M E L

M A C



MAC instructions

Single step (signed) MAC– Integer– Fractional

(Signed) Convolution– Integer

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–

Diff between MAC and convolution– In control path, not shown here



Double-Precision Arithmetic

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Double-Precision Arithmetic in MAC

No. Specifications on the result

D1 Double-precision data add/sub double-precision data Saturate(ACRx[39:0] ± ACRy[39:0])

D2 Double-precision data add/sub single-precision data align to LSBSaturate (ACRx[39:0] ± {24’b OPB [15],OPB[15:0]})

D3 Double-precision data add/sub single-precision data align to MSB

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Saturate (ACRx[39:0] ± {8’b OPB [15],OPB[15:0], 16’b0})D4 Double-precision data plus/sub single precision immediate Saturate

(ACRx[39:0] ± 24’b immediate[15], immediate[15:0])

D5 Absolute operation on a double-precision data if ACRx[39] Saturate

(INV(ACRx[39:0]) + “1”) else ACRxD6 Compare two double-precision data and set flags set flag: Saturate

(ACRx [39:0] - ACRy [39:0])

D7 Simple scale by MUX instead of by shift logic



Scaling in DSP :: MAC

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G 6 4 2

i s i o n A r i t h m e t i c

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M E L

W i t h D o u

b l e P r e



G 6 4 2

S i g n a l s

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M E L

C o n

t r o l



Move / change data types

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Move data from MAC and to MAC

Basic load– Loads in half ACRn and keeps another half.

o The higher part and fill in guards– Loads in half ACRn and cleans another half.

o The higher part and fill in guards

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– Loads in both lower higher part of ACRn.o To fill in guards using the higher part sign



Move data to MAC

Specifications on the result

L1 ACRn <= {8’bA[15],A[15:0], ACRn[15:0]} //Keep lower part

L2 ACRn <= {8’bA[15],A[15:0], 16’H0000} //clean lower part

L3 ACRn <= {ACRn [39:16], A[15:0]} //keep higher part

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n <= , : s gn extens on g er part

L5 ACRn <= {8’bA[15],A[15:0], B[15:0]}// Load A and B from RF

L6 ACRn <= {A[7:0], ACRn[31:0]} // restore guards



Move data to MAC: Logic

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G 6 4 2

o d i f i e d

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M E L

M A C M



Move data from MAC

Specifications on the result

1 Rn <= ACRn[31:16] //Rn is a register in RF

2 Rn <= ACRn[15:0] //Rn is a register in RF

3 Rn <= ACRn[31:16]; Rn+1 <= ACRn [15:0] //Rn and Rn+1 in RF

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4 M1 <= ACRn[31:16]; M2 <= ACRn[15:0]; //M1 M2: memories5 Rn <= ACRn[31:16]; Rn+1<=ACRn[15:0]; Rn+2<=ACRn[39:32]

6 Rn <= {8’h00, ACRn[39:32]}; // guard to register file RF



MAC integration

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Flags in MAC

Usually control code is implemented using ALUinstructions– Flags in MAC is not used much

Mainly for exception– MAC has

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o

Saturation Flag (FMO)o Sign Flag (FMS)o Zero Flag (FMZ)



Data operation Sepuence

Very important– Add guard bits– Operation (iteration) and scaling– Round after iteration– Saturation and removing guard bits

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– Truncation and output



Physical critical path

What is physical critical path?

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D-mem 1 D-mem 2 D-mem 3 D-mem4 ConstantRF OPA

32 to1

RF OPB

32 to1

Long wires Long wires

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As MAC input Very heavy fan out here!

h l l h




ACR1

ACR2ACRm

Registerselectlogic

Dataselectlogic……

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Heavy fan out forMACinternal logic

Long wireFromRF Data memory

Pi li



Pipeline

ACR

*

ACR

*

ACR*

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(a) MAC in one clock cycle (b) MAC using two clocks

Accumulator

Flag circuit

(a) MAC using three clocks

Accumulator

Flag circuit

Accumulator

Flag circuit

E l MAC D i



Example :: MAC Design

Design a MAC unit capable of the following operations:o OP0: No operationo OP1: ACR = 0o OP2: ACR = A * B (Fractional multiplication (signed))o OP3: ACR = A * B + ACR (Fractional multiplication (signed))o OP4: ACR = 1.25 * ACR (Scaling)o OP5: Load ACR with a fractional value from a registero OP6: ACR = SATURATE(ROUND(ACR))

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o : = :o OP8: RF = ACR[15:8]o OP9: RF = SIGNEXTEND(ACR[19:16])

Constraints:

•A and B are 8 bits, registers are 8 bits•ACR is 20 bits (including 4 guard bits).•Only one multiplier may be used. You should select as small a multiplier asnecessary. You also need to annotate whether it is signed or unsigned.

E l MAC D i




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E l MAC D ig




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The End :: Thank you for your attention



The End :: Thank you for your attention

Questions?

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lecture asip 8, 9

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