lecture asip 5

7/28/2019 Lecture ASIP 5

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VLSI Architecture :: MEL G642

MEL G642

Dr. A. Amalin Prince

BITS Pilani K.K. Birla Goa Campus

Department of Electrical , Electronics and Instrumentation Engineering


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System on a chip

What is a DSP core?

What is a DSP processor?

What is a DSP subsystem?

MCU is the task controller-executes tasks without real-time

requirements

MEL G642

MCU subsystemDSP subsystem

DSP Processor core

RF Control path

DM PM Interrupt TimerDMA MMU

CustomerIF

ALU MAC

Bus with arbitration

Main memories

MCU core

AGU

SoCdesignhierarchy

CustomerIF


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G642

rchite

cture

Bus and arbiration

MMU

Main memories

RF Control pathADG

DM DM PMDMA

ubsys

tem

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ME

L

Processor

DSP Processor

DSP core

Interrupt TimerOther pheriph

Chip inferface

ALUMAC accelerator DSP


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Architecture and microarchitecture

The processor architecture is the hardware organization

of the core and its peripherals including the memory bus

architecture. Architecture represents relations of modules The microarchitecture design is the specification of

functional modules

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ASIP microarchitecture design is the implementation ofan ISA specification into hardware modules.


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Inside a core

The core can be divided into three parts:

the datapath, the control path, and the address generation unit

(AGU). The core components are organized around two data

busses:

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The memory bus is distributed between the core and thememory subsystem.

The register bus connects the register file to all units in the core.


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Memory subsystem in a DSP subsystem

The memory subsystem consists of

data memories (DM),

program (code) memory (PM), AGU, DMA, and MMU.

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Peripherals in a DSP subsystem

Timers for counting clock cycles and events

Interrupt controller for handling interrupts

DMA (Direct Memory Access) controller for handlingdata transfers to/from main memory and between other

memories/ports

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MMU (Memory Management Unit) for reliable andefficient (address space) memory usage


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DSP memory architecture

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History of DSP memory architectures

Memory

Control Arithmetic

Programmemory Datamemory

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un un t

In-out

(a) Von Neumann architecture

Controlunit Arithmeticunit

In-out

(b) Harvard architecture


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History of DSP memory architectures

DP DM

CP PM

DP DM

CP PM

MUX

DP DM

CP PM

MUX

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(a) (b) (c)

One tap of

convolution requires

multiple clock

Fetch coefficients

instead of

instructions during

CONV

Dual port/multi-port

memory required.

Used up to 1980s


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A typical DSP bus architecture

Register _File ALU MAC

OPA

OPB

ressingpath

(AGU)

Register

bus

Datapath

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-a ress

D1-data

D2-address

D2-data

P-address

Program

PM DM1 DM2ControlPa

th(CP)andadd

Memorybu

s

PMbus


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Control flow of DSP ASIP

Calculate PC Request an instruction Receive an instruction

Send PC

to PM

Get code

from PMreset

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Receive states from DP Generate operandaddresses

Decode the instructionand send control to DP

Control

signals to DPGenerated addressto storage units

Flags

from DP

Instruction Flow FSM


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Data flow of DSP ASIP

Receiveinstruction

Receive operand

address

Fetch

operands

From PMFrom address

generatorSend address

to storage HW

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Return

statesStore

result

Execute

instruction

Flags toPC FSM

Send result to

storage HW

Data Flow FSM


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G642

faDSP

processor

RF

UPCFSM

PM

Program

address

gura

tion

status

xecun

itALU

/MAC

Instruction

Program flow control

Results

struc

tion

dec

oder

Operand

&

result

co

ntrol

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MEL

Acompleteview

o

A

Con

fi

an

d

D

Operation ctrl

MEM ctrl

Legend

Data bus Control signals

Memory busInternal signals

in control path

I


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Modules in a core

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Modules in a DSP core

Datapath

Register file

ALU MAC

AGU

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Control path


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Differences between design of DSP and MPU

The MPU designers think ofultimate performance and

ultimate flexibility as well as the compiler-friendly

instruction set. The ASIP DSP designers think ofapplication and cost

first, and the challenge is to be efficient.

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The goal of an ASIP design is to reach the highestperformance over silicon, the highest performance over

power consumption, the highest performance over the

design cost.


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Is DSP CISC or RISC

a DSP, like a RISC:

More general-purpose registers.

Most instructions as simple instructions. Instruction decoding by decoding logic circuit instead of

microcode.

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egu ar ns ruc on p pe n ng.

a DSP, like a CISC:

One execution cycle for ALU and multiple cycles for iteration. Complicated data memory addressing modes and circuits.

Special-purpose registers (accumulator registers).

Strong instructions for accelerating certain tasks.


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Is DSP CISC or RISC

DSP RISC CISC

Emphasis on hardware

and software

Emphasis on software Emphasis on hardware

Single and multiclockcomplex instructions Single-clock, reduced instructiononly Includes multiclockcomplex instructions

Operands from registers

Operands also from

Operands only from registers

LOAD and STORE are used to

Arithmetic computing based

on memory-to-memory

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data memories

- -

register variables

Small code size Large code size Small code size

Most silicon area used for

program and data storing

Most silicon area used for

program and data storing

Silicon might be used for

storing complex instructions

(microcode)


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Design instruction set

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G642

tdesi

gnflow

S ource code profiling: c overage and 10-90% lo cality

D esign o f ge neral R ISC instructio ns

D esign of C ISC accele rate d ins tructions

De sig n of mi sc ellaneous ins tructions

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MEL

Instru

ctions

Instruc tion s et simu la tor and a ssem bler

Benc hmarking performa nce a nd covera ge

Release the ins truc tion set archi tec ture

N o

ye s

ns t ruc t on c o ng an r e ea se manua

satisfied


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Release an instruction set

Design of

assembly

instruction set

Instruction set

benchmarkingApplication

profiling

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When

Benchmarking result equivalent to requirements


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We need to identify problems

How is an instruction set designed and why is it designed

in that way?

In which circumstances should a function beimplemented using an instruction instead of a subroutine?

Why ASIP DSP instructions not really RISC

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Why my benchmarking is not satisfactory?


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What is the starting point

Let us start at the point to implement C functions to an

assembly instruction set

A typical architecture with two DM in parallel Instructions including move-load-store, ALU/MAC, and

program flow control

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Classify the Instruction set

Instruction

group /type

Operands Operations Mathematical

description

Flags CC

Load, store,

and move

Register name

and memoryaddressing

Data transfer

and addressingmodes

DST (ADR)


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Move-load-store instructions

RISC processor architecture simple.

Data and parameters of a subroutine are loaded to the

register file first. Operands are from register file or immediate data carried

by an instruction.

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Results in the register file need to be moved back to thedata memory


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Move-load-store instructions

Mnem Operand Description Operation CC

Load Rd, DA Load data from memory

0/1

RdDM(DA) 1

Store DA, Rs Store data to memory

0/1

DM(DA) Rs 1

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move Rd, Rs Move between two

registers

Rd Rs 1

move Rd, K Move immediate data to

a register

Rd immediate 1


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Addressing for data memory access

Memory addressing is addressing algorithm carried by anassembly instruction.

It specifies the way to calculate the memory the uniquelocation of data in a data memory for a read or a write.

MEL G642

Implicitly addressing algorithm in C; explicitly algorithmin ASM


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Addressing for data memory access

Name DA DA code

cost (b)

Memory Algorithm CC

Direct D 16 DM0/1 16-bit constant as the direct

memory address

1

Register

indirect

R 5 DM0/1 A register containing the memory

address

1

=

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incremental

,

addressingRegister

decrement

--R 5 DM0/1 R=R1 before addressing, R gives

address

1


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Arithmetic logic instructions

Basic arithmetic operations in C are +, , , /, and %.

The modulo operation % is not used very often for DSP

arithmetic computing, to implement it using a subroutine. Division operation / is not easy to implement in

hardware

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Basic Arithmetic Instructions

Mnem Operand Description Operation Flags CC

ADD Rd, Rr Add Rd Ra + Rb Z,N,V 1

SUB Rd, Rr Subtract Rd Ra - Rb Z,N,V 1

ABS Rd, Rr Absolute operation RdABS(Ra) Z,N,V 1

INC Rd Increment Rd Ra + 1 Z,N,V 1

DEC Rd Decrement Rd Ra - 1 Z,N,V 1

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MPL A, Rd, Rr Multiplication A

Ra Rb Z,N,V 1MAC A, Rd, Rr Multiplication and

accumulation

AA + Ra Rb Z,N,V 2

RND Rd, A Round, saturate,

and truncate

Rd Saturate(Round(A)) Z,N,V 1

CAC A Clear an

accumulator

A 0 Z,N,V 1


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Logic and Shift Operations

Logic and shift operations in C

&(and), |(or), ~(not), ^(xor),

> (right shift).

Here "and" operates on each bit of operand A and B; that

is, C[0]=A[0] & B[0], C[1]=A[1] & B[1],

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C[15]=A[15] & B[15].

L i d Shif O i


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Logic and Shift Operations

Mnem Operand Description Operation Flags CC

AND Ra, Rb A logic-and B Rd Ra and Rb C, Z 1

OR Ra, Rb A logic-or B Rd Ra or Rb C, Z 1

NOT Ra, Rb Invert A Rd INV (Ra) C, Z 1

XOR Ra, Rb A logic-xor B Rd Ra xor Rb C, Z 1

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LS Ra, Rb Logic left shift Rd Ra left shifted byRb [3:0]

C, Z 1

RS Ra, Rb Logic right shift Rd Ra right shifted by

Rb [3:0]

C, Z 1

L i O i C


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Logic Operators in C

Condition symbol Conditions

< Less than

= Greater than or equal to

> Greater than

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!= Not equal to

&& Boolean AND

|| Boolean OR

! Boolean NOT

P fl t l i C


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Program flow control in C

Conditional and unconditional controls in C. Unconditional GOTO operations.

Conditional: Condition test and jump in C are integrated, for

example, if A then B else C.

In an assembl lan ua e

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Condition test and condition jump are separated the first instruction offers and flag computation

the second instruction is the conditional jump

P fl t l i t ti


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Program flow control instructions

Mnem Description Condit

ions

Flags

meet

CC

JLT Jump when Less than < N=1 3/1

JLE Jump when Less than or Equal to N=0 and

Z=0

3/1

JNE Jump when Not Equal to != Z=0 3/1

JUMP Unconditional jump 3

CALL Jump, push return address into stack 3

Return Return to the stacked address 3

Target addressing for jumping


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Target addressing for jumping

TA Algorithm

Absolute 16 bits constant

Relative In a general register

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y


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G642

ionSe

tSumm

ary

MEL G642

M

EL

A

ssembl

yInstru

c


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Benchmarking theinstruction set

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What is benchmark


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What is benchmark

DSP benchmarking gets cycle cost and code size used by

a DSP algorithm with single-precision data.

Convention of DSP benchmarking round is required before moving long data from an accumulation

register to a general register

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How to benchmark


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How to benchmark

BDTI benchmarking convention

It measures the execution time (cycle cost), the code size

(program memory cost), and the cost of data memories.

The cycle cost = prologue + Kernel + epilogue

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Prologue: preparing for running a program,

Epilogue: terminating the program

Kernel: the part of the algorithm

Assumption in this discussion


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Assumption in this discussion

Data frame size: 40 samples.

The number of FIR taps = 16.

The cycle cost = 1 cycle per normal instruction 3 cyclesfor jump taken.

MAC takes one c cle if the followin instruction does

MEL G642

not use the data in an accumulator register. TSMD: a typical single MAC DSP (TSMD)

processor available as a COTS (commercial off-the shelf).

Example: Block Transfer


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C-code: DM1 (SEG: 0 to 39) -> DM1 (SEG: 0 to 39)

Assembly code

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Processor Algorithm Total cycle

cost

Pro-epilogue

cycle cost

Kernel

cycle cost

Total code

cost

Code for pro-

epilogue

DM

cost

Basic (ours) BT 242 4238

8 4 84

TSMD 47 4

437 4 84

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The loop: The extra cost of each jump taken and DEC of theloop counter consumes four clock cycles. HW loop may

eliminate the cost.

Load and store can be merged to a memory move to memoryinstruction.

Example: Single sample FIR


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Modulo addressing

FIFO Emulated in a data memory

Can be hardware accelerated memory addressing (for accelerated

instructions)

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Example: consider 7-tap FIR Filter


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Example: consider 7 tap FIR Filter

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p g p

Assembly code

MEL G642

Example: Single sample FIR: FIFO behavior


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p g p

DM X (n-3)X (n-4)

X (n)

DARX (n-4)

X (n)

X (n-1)

MIN address

DAR

BAR BARStep 0 Step 1

MEL G642

Thed

atamemoryspace

TAR

BAR

TheFIFO

buffer

BAR + 0

BAR + 1

BAR + 2

BAR + 3

BAR + 4

X (n-1)

X (n-2)

X (n-2)

X (n-3)

Example: The procedure a FIFO getting a new data sample

before getting

new data

MAX address

after getting

new data 1

X (n)

X (n-1)X (n-2)

X (n-3)

X (n-4) DAR

X (n-1)

X (n-2)X (n-3)

X (n-4)

X (n)

after getting

new data 2

DAR

after getting

new data 3

TAR TAR

TAR

BAR

TAR

BAR

Step 2 Step 3

Example: N sample FIR (Single Sample inloop)


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loop)

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p g p

Processor Algorithm Total cycle cost Kernel cycle

cost

Total code

cost

Basic 16-tapFIR 192 173 26

TSMD 16-tapFIR 31 16 15

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- . .

times higher than the benchmark of a TSMD. Opportunities for improvement are:

The cost ofSW emulated circular buffer and modulo addressing is high.

o HW circular buffer and modulo addressing is essential.

Data and coefficient loading, MAC, and the loop control can be merged into

one instruction, convolution, which is one of the most frequently used

instructions in DSP.

CONV N DM0(AP0++M) DM1(AP1++)

Example:


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p

FIR Filtering

Auto correlation Autocorrelation is used for finding regularities or periodical

features of a signal

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Cross-correlation

Cross-correlation is used for measuring the similarity of a signal

with a known signal pattern

What difference??


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Analyses on identifiedproblems

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Lessons Learned


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C does not give parallel features;

The convolution is one of the most used DSP operations, very high

efficiency by having the memory addressing, arithmetic

computing, result store, and program flow control carried out inparallel in one instruction.

It is ossible because the arallel hardware can be or anized in a

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pipeline.

Other most frequently used iterative DSP ops can also be

specified into one instruction.

Research work: Why?

Identify the requirement and benchmark it

Conclusion


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An assembly language instruction set must be more

efficient.

Accelerations implemented at arithmetic and algorithmic

levels.

Addressing and memory accesses should be executed in

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parallel with arithmetic computing. Program flow control such as loop or conditional execution

shall also be accelerated

ASIP microarchitecture design flow


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Proposed assembly language manual

pe

line

Further expose all micro operations of each assembly instruction

Partiton micro operations into DP, CP, and AP

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Propose

dp

steps

Schedule micro operations into each pipeline step

Design for HW multiplexing in DP and AP

Specify microarchitecture and micro operations for CP

Release micro architecture documents

The End :: Thank you for your attention


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Questions?

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