rangkain sekuensial
TRANSCRIPT
![Page 1: Rangkain Sekuensial](https://reader033.vdokumen.com/reader033/viewer/2022042423/552031bc497959842f8b4891/html5/thumbnails/1.jpg)
RangkaianRangkaian Digital Digital
Synchronous Sequential Synchronous Sequential
LogicLogic
swj/08swj/08 11
Adapted from : C. Gerousis, © Digital Design 3rd Ed.,
Mano,Prentice Hall
![Page 2: Rangkain Sekuensial](https://reader033.vdokumen.com/reader033/viewer/2022042423/552031bc497959842f8b4891/html5/thumbnails/2.jpg)
Sequential Logic
Sebuah sistem digital dapat merupakan combinational logic atau sequential
logic. Jenis yang kedua memiliki elemen penyimpanan.
feedback path
swj/08swj/08 22
feedback path
� Informasi yang disimpan dalam elemen memory pada suatu saat menentukan
keadaan dari rangkaian sequential pada saat itu.
� Rangkaian sequential menerima informasi dari input eksternal. Input-input ini
bersama dengan keadaan saat ini dari elemen penyimpan, menentukan nilai dari
output.
![Page 3: Rangkain Sekuensial](https://reader033.vdokumen.com/reader033/viewer/2022042423/552031bc497959842f8b4891/html5/thumbnails/3.jpg)
Synchronous Sequential Logic
� Rangkaian synchronous sequential adalah sistem yang
perilakunya dapat ditentukan dari pengetahuan tentang
sinyalnya pada waktu diskret.
� Sinkronisasi dilakukan oleh clock generator yang memberikan
serangkaian pulsa clock secara periodik.
swj/08swj/08 33
� Elemen penyimpan yang digunakan dalam rangkaian
sequential yang menggunakan clock disebut flip-flops.
� Sebuah flip flop adalah peralatan penyimpan yang mampu
menyimpan satu bit informasi.
![Page 4: Rangkain Sekuensial](https://reader033.vdokumen.com/reader033/viewer/2022042423/552031bc497959842f8b4891/html5/thumbnails/4.jpg)
Synchronous Clocked Sequential Logic
swj/08swj/08 44
Output diperoleh dari rangkaian kombinasional atau dari flip-flops atau
keduanya. Flip-flops menerima input dari rangkaian kombinasional dan sinyal
clock. Keadaan flip-flops hanya dapat berubah selama transisi pulsa clock.
![Page 5: Rangkain Sekuensial](https://reader033.vdokumen.com/reader033/viewer/2022042423/552031bc497959842f8b4891/html5/thumbnails/5.jpg)
LATCHES
Tipe paling dasar dari flip-flop adalah latch yang bekerja dengan sinyal level.
Latch adalah building blocks dari flip-flops.
swj/08swj/08 55
Dalam kondisi normal, kedua input latch tetap 0 kecuali keadaan berubah.
Jika S = 1� latch dalam keadaan ‘set’ : Q = 1, Q’ = 0.
Sebelum R reset ke 1, S harus kembali ke 0 untuk menghindari
kemunculan dari keadaan tak tentu dimana kedua output = 0
undefined state
![Page 6: Rangkain Sekuensial](https://reader033.vdokumen.com/reader033/viewer/2022042423/552031bc497959842f8b4891/html5/thumbnails/6.jpg)
SR LATCH with NAND )''( RS
undefined state
swj/08swj/08 66
• SR latch dengan gerbang NAND memerlukan sinyal 0 untuk
berubah keadaan.
• Sinyal input untuk NAND-latch adalah komplemen dari nilai
yang digunakan untuk NOR latch.
undefined state
![Page 7: Rangkain Sekuensial](https://reader033.vdokumen.com/reader033/viewer/2022042423/552031bc497959842f8b4891/html5/thumbnails/7.jpg)
SR LATCH with Control Input
swj/08swj/08 77
• Input kontrol C menentukan kapan keadaan dari latch boleh berubah
• Jika C = 0, output dari gerbang NAND tetap 1 � State tidak berubah
• Jika S = 1, R = 0, C = 1 � ‘set’
• Jika S = 0, R = 0, C = 1 � State tidak berubah
• Jika S = 0, R = 1, C = 1 � ‘reset’
![Page 8: Rangkain Sekuensial](https://reader033.vdokumen.com/reader033/viewer/2022042423/552031bc497959842f8b4891/html5/thumbnails/8.jpg)
D LATCH
swj/08swj/08 88
D latch mengurangi kondisi tak diharapkan dari keadaan tak tentu
yang muncul dalam SR latch (Q = Q’ = 1).
Jika D = 1, Q = 1 � ‘set’
Jika D = 0, Q = 0 � ‘reset’
![Page 9: Rangkain Sekuensial](https://reader033.vdokumen.com/reader033/viewer/2022042423/552031bc497959842f8b4891/html5/thumbnails/9.jpg)
Symbols for Latches
swj/08swj/08 99
![Page 10: Rangkain Sekuensial](https://reader033.vdokumen.com/reader033/viewer/2022042423/552031bc497959842f8b4891/html5/thumbnails/10.jpg)
Flip-Flops
• State pada latch dan flip-flop berubah karena perubahan sinyal
kontrol (trigger)
•D-latch di-trigger setiap kali pulsa menjadi high atau level logic
“1”.
swj/08swj/08 1010
• Selama pulsa input tetap pada level ini, setiap perubahan pada
input data akan mengakibatkan perubahan output dan state dari
latch.
• Flip-flop di-trigger pada saat transisi sinyal pada input kontrol,
dari 0 ke 1 (positive-edge trigger) atau dari 1 ke 0 (negative-
edge trigger).
![Page 11: Rangkain Sekuensial](https://reader033.vdokumen.com/reader033/viewer/2022042423/552031bc497959842f8b4891/html5/thumbnails/11.jpg)
Positive level
swj/08swj/08 1111
Positive-edge triggered
Negative-edge triggered
![Page 12: Rangkain Sekuensial](https://reader033.vdokumen.com/reader033/viewer/2022042423/552031bc497959842f8b4891/html5/thumbnails/12.jpg)
Edge-Triggered Flip-Flop
swj/08swj/08 1212
Rangkaian mempunyai input D dan merubah outputnya pada saat negative side
dari clock, CLK.
Jika CLK“0”, output inverter “1”. Latch slave enabled dan output Q sama
dengan output master, Y. Latch master disabled (CLK = 0).
Jika CLK berubah ke high, input D ditransfer ke latch master. Slave tetap
disabled selama C low. Setiap perubahan input merubah Y, tetapi tidak Q.
Output flip-flop dapat berubah jika CLK mengalami transition 1� 0∴
![Page 13: Rangkain Sekuensial](https://reader033.vdokumen.com/reader033/viewer/2022042423/552031bc497959842f8b4891/html5/thumbnails/13.jpg)
Edge-Triggered Flip-Flop: Graphic Symbols
swj/08swj/08 1313
Flip-flop yang paling ekonomis dan efisien adalah edge-triggered
D flip-flop karena membutuhkan jumlah gerbang paling sedikit.
![Page 14: Rangkain Sekuensial](https://reader033.vdokumen.com/reader033/viewer/2022042423/552031bc497959842f8b4891/html5/thumbnails/14.jpg)
JK Flip-Flop
swj/08swj/08 1414
JK flip-flop mampu menampilkan : set ke 1, reset ke 0, atau
mengkomplemen output:
1. Input J men-set flip-flop ke 1.
2. Input K me-reset flip-flop ke 0.
3. Jika J dan K enabled, output dikomplemen.
![Page 15: Rangkain Sekuensial](https://reader033.vdokumen.com/reader033/viewer/2022042423/552031bc497959842f8b4891/html5/thumbnails/15.jpg)
JK Flip-Flop
swj/08swj/08 1515
Jika J = 1 dan K = 0, D = 1� next clock edge sets output to 1.
Jika J = 0 dan K = 1, D = 0� next clock edge resets output to 0.
Jika J = 1 dan K = 1, D = Q’� next clock edge complements output.
Jika J = 0 dan K = 0, D = Q� next clock edge leaves output unchanged.
QKJQD ''+=
![Page 16: Rangkain Sekuensial](https://reader033.vdokumen.com/reader033/viewer/2022042423/552031bc497959842f8b4891/html5/thumbnails/16.jpg)
T Flip-Flop
T (toggle) flip-flop adalah flip-flop komplemen dan dapat
diperoleh dari JK flip-flop bila kedua inputnya disatukan.
Jika T = 0�
D = Q dan tidak ada perubahan output
QQTD =⊕=
Jika T = 1�
D = Q’ dan output adalah komplemennya
'QQTD =⊕=
swj/08swj/08 1616
D = Q’ dan output adalah komplemennya
![Page 17: Rangkain Sekuensial](https://reader033.vdokumen.com/reader033/viewer/2022042423/552031bc497959842f8b4891/html5/thumbnails/17.jpg)
Characteristic Tables and Equations
J K Q(t+1)
0 0 Q(t) No change
0 1 0 Reset
1 0 1 Set
1 1 Q’(t) Complement T Q(t+1)
0 Q(t) No changeQKJQtQ '')1( +=+
Q(t) = present state
Q(t+1) = next state after one clock period
swj/08swj/08 1717
D Q(t+1)
0 0 Reset
1 1 Set
0 Q(t) No change
1 Q’(t) Complement
DtQ =+ )1(
QTTQQTtQ '')1( +=⊕=+
QKJQtQ '')1( +=+
![Page 18: Rangkain Sekuensial](https://reader033.vdokumen.com/reader033/viewer/2022042423/552031bc497959842f8b4891/html5/thumbnails/18.jpg)
Analysis of Clocked Sequential Circuits
Kelakuan dari rangkaian sequential dengan clock ditentukan oleh
input, output, dan state flip-flop.
� State Equation
State equation (transition equation) menentukan next state sebagai
fungsi dari present state and input.
swj/08swj/08 1818
fungsi dari present state and input.
� State Table
State table (transition table) terdiri dari: present state, input
next state dan output.
� State Diagram
Informasi dalam state table dapat direpresentasikan secara grafis dengan
state diagram. State dinyatakan dengan lingkaran dan transisi antar
state dinyatakan dengan garis berarah yang menghubungkan kedua lingkaran.
![Page 19: Rangkain Sekuensial](https://reader033.vdokumen.com/reader033/viewer/2022042423/552031bc497959842f8b4891/html5/thumbnails/19.jpg)
1. Tentukan persamaan input flip-Flop dalam present state dan
variabel input.
Analysis Procedure
Analysis of Clocked Sequential Circuits
swj/08swj/08 1919
2. Substitusikan persamaan input kedalam persamaan karakteristik
flip-flop untuk memperoleh persamaan state.
3. Gunakan persamaan state yang sesuai untuk menentukan nilai
next state dalam state table.
![Page 20: Rangkain Sekuensial](https://reader033.vdokumen.com/reader033/viewer/2022042423/552031bc497959842f8b4891/html5/thumbnails/20.jpg)
Example of a Sequential Circuit
)(')]()([
)()(')1(
)()()()()1(
txtBtAy
txtAtB
txtBtxtAtA
+=
=+
+=+
State Equations
(t+1)� next state of the flip-flop
one clock edge later.
swj/08swj/08 2020note mistake in Fig. 5-15 p. 181
xAtB
BxAxtA
')1(
)1(
=+
+=+
')( xBAy +=
Flip-flop input equations
(excitation equations)
xAD
BxAxD
B
A
'=
+=
![Page 21: Rangkain Sekuensial](https://reader033.vdokumen.com/reader033/viewer/2022042423/552031bc497959842f8b4891/html5/thumbnails/21.jpg)
Example of a Sequential Circuit (continued)
Present Next
State Input State Output
A B x A B y
0 0 0 0 0 0
xAtB
BxAxtA
')1(
)1(
=+
+=+
')( xBAy +=
swj/08swj/08 2121
0 0 0 0 0 0
0 0 1 0 1 0
0 1 0 0 0 1
0 1 1 1 1 0
1 0 0 0 0 1
1 0 1 1 0 0
1 1 0 0 0 1
1 1 1 1 0 1
![Page 22: Rangkain Sekuensial](https://reader033.vdokumen.com/reader033/viewer/2022042423/552031bc497959842f8b4891/html5/thumbnails/22.jpg)
Present Next
State Input State Output
A B x A B y
0 0 0 0 0 0
0 0 1 0 1 0 a0 1 0 0 0 1
0 1 1 1 1 0 b a
c
Example of a Sequential Circuit (continued)
swj/08swj/08 2222
0 1 1 1 1 0 b1 0 0 0 0 1
1 0 1 1 0 0 c1 1 0 0 0 1
1 1 1 1 0 1
a
a: Saat rangkaian sequential dalam present state 00 dan input 1, output 0.
Setelah siklus next clock, rangkaian menuju next state 01.
b: saat rangkaian sequential dalam present state 01 dan input 1, output 0.
Setelah siklus next clock, rangkaian menuju next state 11.
c: Tidak ada perubahan state
Mealy model
![Page 23: Rangkain Sekuensial](https://reader033.vdokumen.com/reader033/viewer/2022042423/552031bc497959842f8b4891/html5/thumbnails/23.jpg)
Sequential Circuit Analysis with D Flip-Flops
yxADA ⊕⊕=
( 1)A t A x y+ = ⊕ ⊕
swj/08swj/08 2323
a
b
( 1)A t A x y+ = ⊕ ⊕
![Page 24: Rangkain Sekuensial](https://reader033.vdokumen.com/reader033/viewer/2022042423/552031bc497959842f8b4891/html5/thumbnails/24.jpg)
BxKBJ AA
⊕==
== '
1. Persamaan input Flip-Flop :
Example of Sequential Circuit with JK Flip-Flops
swj/08swj/08 2424
xAKxJ BB ⊕== '
![Page 25: Rangkain Sekuensial](https://reader033.vdokumen.com/reader033/viewer/2022042423/552031bc497959842f8b4891/html5/thumbnails/25.jpg)
2. Substitusikan persamaan input kedalam persamaan karakteristik
flip-flop untuk memperoleh persamaan state.
'')1( AKAJtA AA +=+ BxKBJ AA == '
Persamaan karakteristik JK Flip-Flop Persamaan input Flip-Flop
Example of Sequential Circuit with JK FF (2)
swj/08swj/08 2525
'''')'( '')1(
'')''( ')1(
'')1(
BxAABxxBBxABxtB
AxABBAABxBAtA
BKBJtB BB
AA
++=⊕+=+
++=+=+
+=+
3. Gunakan persamaan state yang sesuai untuk menentukan nilai
next state dalam state table.
xAKxJ BB
AA
⊕== '
Persamaan state rangkaian sequential
![Page 26: Rangkain Sekuensial](https://reader033.vdokumen.com/reader033/viewer/2022042423/552031bc497959842f8b4891/html5/thumbnails/26.jpg)
Present Next Flip-Flop
State Input State Inputs
A B x A B
0 0 0 0 1 0 0 1 0
0 0 1 0 0 0 0 0 1
0 1 0 1 1 1 1 1 0
0 1 1 1 0 1 0 0 1
BBAA KJKJ
Example of Sequential Circuit with JK FF (3)
swj/08swj/08 2626
1 0 0 1 1 0 0 1 1
1 0 1 1 0 0 0 0 0
1 1 0 0 0 1 1 1 1
1 1 1 1 1 1 0 0 0
'''')'( '')1(
'')''( ')1(
BxAABxxBBxABxtB
AxABBAABxBAtA
++=⊕+=+
++=+=+
![Page 27: Rangkain Sekuensial](https://reader033.vdokumen.com/reader033/viewer/2022042423/552031bc497959842f8b4891/html5/thumbnails/27.jpg)
Example of Sequential Circuit with T Flip-Flops
ABy
xT
BxT
B
A
=
=
=
1. Flip-Flop input equations:
swj/08swj/08 2727
![Page 28: Rangkain Sekuensial](https://reader033.vdokumen.com/reader033/viewer/2022042423/552031bc497959842f8b4891/html5/thumbnails/28.jpg)
2. Substitusikan persamaan input equations kedalam persamaan
karakteristik flip-flop untuk memperoleh persamaan state.
xT
BxTA
=
=
TQQTQTtQ '')1( +=⊕=+
Persamaan input Flip-Flop
Persamaan karakteristik T Flip-Flop
Example: T Flip-Flops circuit (2)
swj/08swj/08 2828
ABy
xTB
=
=
BxtB
BxAAxABABxABxtA
⊕=+
++=+=+
)1(
' ' ')'()'()1(
Persamaan input Flip-Flop
Persamaan state
rangkaian
sequential
![Page 29: Rangkain Sekuensial](https://reader033.vdokumen.com/reader033/viewer/2022042423/552031bc497959842f8b4891/html5/thumbnails/29.jpg)
Present Next
State Input State Output
A B x A B y
0 0 0 0 0 0
0 0 1 0 1 0
0 1 0 0 1 0
0 1 1 1 0 0
1 0 0 1 0 0
Example: T Flip-Flops circuit (3)
swj/08swj/08 2929
BxtB
BxAAxABABxABxtA
⊕=+
++=+=+
)1(
' ' ')'()'()1(
1 0 0 1 0 0
1 0 1 1 1 0
1 1 0 1 1 1
1 1 1 0 0 1
![Page 30: Rangkain Sekuensial](https://reader033.vdokumen.com/reader033/viewer/2022042423/552031bc497959842f8b4891/html5/thumbnails/30.jpg)
State Reduction
Goal: reduce the number of states while keeping the external
input-output requirements unchanged.
State reduction example:
a: input 0 � output 0, circuit stays in same state a
a: input 1 � output 0, circuit goes to state b
b: input 0 � output 0, circuit goes to state c
swj/08swj/08 3030
b: input 0 � output 0, circuit goes to state c
c: input 1 � output 0, circuit goes to state d
![Page 31: Rangkain Sekuensial](https://reader033.vdokumen.com/reader033/viewer/2022042423/552031bc497959842f8b4891/html5/thumbnails/31.jpg)
State Reduction
Present State Next State Output
x = 0 x = 1 x = 0 x = 1
a a b 0 0
b c d 0 0
c a d 0 0
d e f 0 1
swj/08swj/08 3131
d e f 0 1
e a f 0 1
f g f 0 1
g a f 0 1
![Page 32: Rangkain Sekuensial](https://reader033.vdokumen.com/reader033/viewer/2022042423/552031bc497959842f8b4891/html5/thumbnails/32.jpg)
Present State Next State Output
x = 0 x = 1 x = 0 x = 1
a a b 0 0
b c d 0 0
State Reduction Algorithm: Two states are equivalent if,
for each member of the set inputs, they give the same output
and send the circuit to the same state or equivalent state.
State Reduction
swj/08swj/08 3232
b c d 0 0
c a d 0 0
d e f 0 1
e a f 0 1
f g f 0 1
g a f 0 1
row with present state g is removed, and state g is replaced by state e each time it
occurs.
equivalent statese
![Page 33: Rangkain Sekuensial](https://reader033.vdokumen.com/reader033/viewer/2022042423/552031bc497959842f8b4891/html5/thumbnails/33.jpg)
Present State Next State Output
x = 0 x = 1 x = 0 x = 1
a a b 0 0
b c d 0 0
State Reduction Algorithm: Two states are equivalent if,
for each member of the set inputs, they give the same output
and send the circuit to the same state or equivalent state.
State Reduction
swj/08swj/08 3333
b c d 0 0
c a d 0 0
d e f 0 1
e a f 0 1
f e f 0 1
row with present state f is removed, and state f is replaced by state d each time it
occurs.
equivalent
states
d
d
![Page 34: Rangkain Sekuensial](https://reader033.vdokumen.com/reader033/viewer/2022042423/552031bc497959842f8b4891/html5/thumbnails/34.jpg)
Present State Next State Output
x = 0 x = 1 x = 0 x = 1
a a b 0 0
b c d 0 0
c a d 0 0
State Reduction
swj/08swj/08 3434
c a d 0 0
d e d 0 1
e a d 0 1
![Page 35: Rangkain Sekuensial](https://reader033.vdokumen.com/reader033/viewer/2022042423/552031bc497959842f8b4891/html5/thumbnails/35.jpg)
Present State Next State Output
x = 0 x = 1 x = 0 x = 1
a 000 a 000 b 001 0 0
b 001 c 010 d 011 0 0
c 010 a 000 d 011 0 0
d 011 e 100 d 011 0 1
State Coded Binary Assignment
swj/08swj/08 3535
d 011 e 100 d 011 0 1
e 100 a 000 d 011 0 1
Reduced State Table with Binary Assignment
![Page 36: Rangkain Sekuensial](https://reader033.vdokumen.com/reader033/viewer/2022042423/552031bc497959842f8b4891/html5/thumbnails/36.jpg)
Sequential Circuits: Design Procedure
Recommended Design Steps
• Tentukan diagram state berdasarkan deskripsi sistem yang diberikan
untuk memenuhi spesifikasi dari operasi yang diharapkan.
• Lakukan penyederhanaan state jika diperlukan.
• Tentukan nilai biner dari tiap-tiap state.
swj/08swj/08 3636
• Tentukan nilai biner dari tiap-tiap state.
• Susunlah tabel state yang sesuai.
• Tentukan tipe flip-flop yang akan digunakan.
• Tentukan persamaan input-ouput flip-flop.
• Gambar diagram logic rancangan.
![Page 37: Rangkain Sekuensial](https://reader033.vdokumen.com/reader033/viewer/2022042423/552031bc497959842f8b4891/html5/thumbnails/37.jpg)
Example : Sequence Detector Sequential Circuit
Design a circuit that detects three or more consecutive 1’s in
a string of bits using D Flip-Flops.
• Start with state S0
• If the input is 0 � circuit stays in the same state
• If the next input is 1 � circuit goes to S to indicate that 1 was detected
swj/08swj/08 3737
• If the next input is 1 � circuit goes to S1 to indicate that 1 was detected
• If the next input is 1 � circuit goes to S2 to indicate that the arrival of two
consecutive 1’s.
• But if the input were 0 � circuit goes back to S0.
• The third consecutive 1 sends the circuit to S3.
• If more 1 are detected � circuit stays in S3.
![Page 38: Rangkain Sekuensial](https://reader033.vdokumen.com/reader033/viewer/2022042423/552031bc497959842f8b4891/html5/thumbnails/38.jpg)
State Diagram
swj/08swj/08 3838
![Page 39: Rangkain Sekuensial](https://reader033.vdokumen.com/reader033/viewer/2022042423/552031bc497959842f8b4891/html5/thumbnails/39.jpg)
Present
State
A B x A B y
Input
Next
State Output
• State table is derived directly from the state diagram.
• We choose 2 D Flip-Flops (outputs A, B)
• There is one input x and one output yD flip-flop state Equations:
)7,6(),,(
)7,5,1(),,()1(
)7,5,3(),,()1(
Σ=
Σ==+
Σ==+
xBAy
xBADtA
xBADtA
B
A
Sequence Detector Sequential Circuit
swj/08swj/08 3939
0 0 0 0 0 0
0 0 1 0 1 0
0 1 0 0 0 0
0 1 1 1 0 0
1 0 0 0 0 0
1 0 1 1 1 0
1 1 0 0 0 1
1 1 1 1 1 1
This state table is the result
of Moore implementation:
�output depends on the
present state only.
![Page 40: Rangkain Sekuensial](https://reader033.vdokumen.com/reader033/viewer/2022042423/552031bc497959842f8b4891/html5/thumbnails/40.jpg)
)7,6(),,(
)7,5,1(),,()1(
)7,5,3(),,()1(
Σ=
Σ==+
Σ==+
xBAy
xBADtA
xBADtA
B
A
• Obtain the simplified functions from the K-Maps:
Sequence Detector Sequential Circuit
swj/08swj/08 4040
![Page 41: Rangkain Sekuensial](https://reader033.vdokumen.com/reader033/viewer/2022042423/552031bc497959842f8b4891/html5/thumbnails/41.jpg)
Sequential Circuit Logic Diagram
swj/08swj/08 4141
![Page 42: Rangkain Sekuensial](https://reader033.vdokumen.com/reader033/viewer/2022042423/552031bc497959842f8b4891/html5/thumbnails/42.jpg)
Excitation table
swj/08swj/08 4242
![Page 43: Rangkain Sekuensial](https://reader033.vdokumen.com/reader033/viewer/2022042423/552031bc497959842f8b4891/html5/thumbnails/43.jpg)
Present
StateInput
Next
State Flip-Flop inputs
A B x A B J A K A J B K B
0 0 0 0 0 0 X 0 X
In order to determine the input equations for the JK flip-flops, it is necessary
to derive a functional relationship between the state table and the input equations.
Synthesis using JK Flip-Flops
swj/08swj/08 4343
0 0 1 0 1 0 X 1 X
0 1 0 1 0 1 X X 1
0 1 1 0 1 0 X X 0
1 0 0 1 0 X 0 0 X
1 0 1 1 1 X 0 1 X
1 1 0 1 1 X 0 X 0
1 1 1 0 0 X 1 X 1
![Page 44: Rangkain Sekuensial](https://reader033.vdokumen.com/reader033/viewer/2022042423/552031bc497959842f8b4891/html5/thumbnails/44.jpg)
Synthesis using JK Flip-Flops
swj/08swj/08 4444
![Page 45: Rangkain Sekuensial](https://reader033.vdokumen.com/reader033/viewer/2022042423/552031bc497959842f8b4891/html5/thumbnails/45.jpg)
Synthesis using JK Flip-Flops
swj/08swj/08 4545
![Page 46: Rangkain Sekuensial](https://reader033.vdokumen.com/reader033/viewer/2022042423/552031bc497959842f8b4891/html5/thumbnails/46.jpg)
Synthesis using T Flip-Flops
swj/08swj/08 4646
K-Map ?