desain flip flop sr, d, jk, dan t

8/20/2019 Desain Flip Flop Sr, d, Jk, Dan t

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1. S-R Flip Flop

The SET-RESET flip flop is designed with the help of two NOR gates and also two NAND

gates. These flip flops are also called S-R Latch.

S-R Flip Flop using NOR Gate

The design of such a flip flop includes two inputs, called the SET [S and RESET [R. There are

also two outputs, ! and !". The diagra# and truth ta$le is shown $elow.

S-R %lip %lop using NOR &ate

%ro# the diagra# it is e'ident that the flip flop has #ainl( four states. The( are

S=1, R=0—Q=1, Q’=0

This state is also called the SET state.

S=0, R=1—Q=0, Q’=1

This state is )nown as the RESET state.


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*n $oth the states (ou can see that the outputs are +ust co#pli#ents of each other and that the

'alue of ! follows the 'alue of S.

S=0, R=0—Q & Q’ = Remember

*f $oth the 'alues of S and R are switched to , then the circuit re#e#$ers the 'alue of S and R in their pre'ious state.

S=1, R=1—Q=0, Q’=0 !n"ali#$

This is an in'alid state $ecause the 'alues of $oth ! and !" are . The( are supposed to $e

co#pli#ents of each other. Nor#all(, this state #ust $e a'oided.

S-R Flip Flop using N%N Gate

The circuit of the S-R flip flop using NAND &ate and its truth ta$le is shown $elow.

S-R %lip %lop using NAND &ate

Li)e the NOR &ate S-R flip flop, this one also has four states. The( are

S=1, R=0—Q=0, Q’=1

This state is also called the SET state.


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S=0, R=1—Q=1, Q’=0

This state is )nown as the RESET state.

*n $oth the states (ou can see that the outputs are +ust co#pli#ents of each other and that the

'alue of ! follows the co#pli#ent 'alue of S.

S=0, R=0—Q=1, & Q’ =1 !n"ali#$

*f $oth the 'alues of S and R are switched to it is an in'alid state $ecause the 'alues of $oth !

and !" are . The( are supposed to $e co#pli#ents of each other. Nor#all(, this state #ust $e

a'oided.

S=1, R=1—Q & Q’= Remember

*f $oth the 'alues of S and R are switched to , then the circuit re#e#$ers the 'alue of S and R

in their pre'ious state.

'lo()e# S-R Flip Flop

*t is also called a &ated S-R flip flop.

The pro$le#s with S-R flip flops using NOR and NAND gate is the in'alid state. This pro$le#can $e o'erco#e $( using a $ista$le SR flip-flop that can change outputs when certain in'alid

states are #et, regardless of the condition of either the Set or the Reset inputs. %or this, a cloc)ed

S-R flip flop is designed $( adding two AND gates to a $asic NOR &ate flip flop. The circuit

diagra# and truth ta$le is shown $elow.


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loc)ed S-R %lip %lop

A cloc) pulse [/ is gi'en to the inputs of the AND &ate. 0hen the 'alue of the cloc) pulse is1", the outputs of $oth the AND &ates re#ain 1". As soon as a pulse is gi'en the 'alue of /

turns 1". This #a)es the 'alues at S and R to pass through the NOR &ate flip flop. 2ut when the

'alues of $oth S and R 'alues turn 1", the 3*&3 'alue of / causes $oth of the# to turn to 1"for a short #o#ent. As soon as the pulse is re#o'ed, the flip flop state $eco#es inter#ediate.

Thus either of the two states #a( $e caused, and it depends on whether the set or reset input of

the flip-flop re#ains a 1" longer than the transition to 1" at the end of the pulse. Thus the in'alid

states can $e eli#inated.

*. Flip Flop

The circuit diagra# and truth ta$le is gi'en $elow.


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D %lip %lop

D flip flop is actuall( a slight #odification of the a$o'e e4plained cloc)ed SR flip-flop. %ro# the

figure (ou can see that the D input is connected to the S input and the co#ple#ent of the D input

is connected to the R input. The D input is passed on to the flip flop when the 'alue of / is 1".

0hen / is 3*&3, the flip flop #o'es to the SET state. *f it is 1", the flip flop switches to theLEAR state.

To )now #ore a$out the triggering of flip flop clic) on the lin) $elow.

+% % OO / +R!GGR!NG OF F! FOS

+% % OO / %S+R-S%2 F! FO '!R'3!+

4. 5- Flip Flop

http://www.circuitstoday.com/triggering-of-flip-flopshttp://www.circuitstoday.com/triggering-of-flip-flopshttp://www.circuitstoday.com/master-slave-flip-flop-circuithttp://www.circuitstoday.com/master-slave-flip-flop-circuithttp://www.circuitstoday.com/master-slave-flip-flop-circuithttp://www.circuitstoday.com/triggering-of-flip-flops


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The circuit diagra# and truth-ta$le of a 5-6 flip flop is shown $elow.

5-6 %lip %lop

A 5-6 flip flop can also $e defined as a #odification of the S-R flip flop. The onl( difference isthat the inter#ediate state is #ore refined and precise than that of a S-R flip flop.

The $eha'ior of inputs 5 and 6 is sa#e as the S and R inputs of the S-R flip flop. The letter 5stands for SET and the letter 6 stands for LEAR.

0hen $oth the inputs 5 and 6 ha'e a 3*&3 state, the flip-flop switch to the co#ple#ent state.So, for a 'alue of ! 7 , it switches to !7 and for a 'alue of ! 7 , it switches to !7.

The circuit includes two 8-input AND gates. The output ! of the flip flop is returned $ac) as a

feed$ac) to the input of the AND along with other inputs li)e 6 and cloc) pulse [/. So, if the


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'alue of / is 1", the flip flop gets a LEAR signal and with the condition that the 'alue of !

was earlier . Si#ilarl( output !" of the flip flop is gi'en as a feed$ac) to the input of the AND

along with other inputs li)e 5 and cloc) pulse [/. So the output $eco#es SET when the 'alueof / is onl( if the 'alue of !" was earlier .

The output #a( $e repeated in transitions once the( ha'e $een co#pli#ented for 5767 $ecauseof the feed$ac) connection in the 56 flip-flop. This can $e a'oided $( setting a ti#e duration

lesser than the propagation dela( through the flip-flop. The restriction on the pulse width can $eeli#inated with a #aster-sla'e or edge-triggered construction.

6. + Flip Flop

This is a #uch si#pler 'ersion of the 5-6 flip flop. 2oth the 5 and 6 inputs are connectedtogether and thus are also called a single input 5-6 flip flop. 0hen cloc) pulse is gi'en to the flip

flop, the output $egins to toggle. 3ere also the restriction on the pulse width can $e eli#inated

with a #aster-sla'e or edge-triggered construction. Ta)e a loo) at the circuit and truth ta$le

$elow.


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T %lip %lop

desain flip flop sr, d, jk, dan t

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