a. judul : flip-flop jk b. c. 1. -...

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1 A. Judul : FLIP-FLOP JK B. Tujuan Kegiatan Belajar 15 : Setelah mempraktekkan Topik ini, anda diharapkan dapat : 1) Mengetahui cara kerja rangkaian Flip-Flop J-K. 2) Merangkai rangkaian Flip-Flop J-K. C. Dasar Teori Kegiatan Belajar 15 1. Flip-flop J-K Kelemahan flip-flop S-R adalah munculnya output yang tidak dapat didefinisikan ketika input S dan R tinggi untuk jenis NOR dan rendah untuk jenis NAND.Untuk menanggulanginya muncul keadaan tersebut,maka dikembangkan flip-flop J-K, flip-flop J-K dibangun untuk mengantisipasi keadaan terlarang pada flip-flop S-R, dan rangaian ditunjukan pada gambar di bawah ini. Gambar 1.1 Logic diagram dan logic simbol IC 7476 Konfigurasi diatas telah dapat menghilangkan keadaan terlarang yang terjadi pada flip-flop S-R.Penggunaan flip-flop J-K dapat menimbulkan masalah apabila sinyal input J dan K diberikan bersamaan dengan sinyal clock pemicu.Misal flip-flop J-K dioperasikan dalam keadaan set,sehingga input diberikan keadaan tinggi ( J = 1) dan inpu K diberikan keadaan rendah (K=0).Perlu dikemukakan terlebih dahulu bahwa pada umumnya sinyal-sinyal pemicu flip-flop termasuk sinyal input ketika diumpankan ke input-input flip- flop tidak langsung bernilai tinggi,namun memerlukan waktu tertentu atau mengalami penundaan dalam mencapai keadaan stabil.

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Page 1: A. Judul : FLIP-FLOP JK B. C. 1. - elektro.um.ac.idelektro.um.ac.id/wp-content/uploads/2016/04/Sistem-Digital-JK.pdf · dikembangkan flip-flop J-K, flip-flop J-K dibangun untuk mengantisipasi

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A. Judul : FLIP-FLOP JK

B. Tujuan Kegiatan Belajar 15 :

Setelah mempraktekkan Topik ini, anda diharapkan dapat :

1) Mengetahui cara kerja rangkaian Flip-Flop J-K.

2) Merangkai rangkaian Flip-Flop J-K.

C. Dasar Teori Kegiatan Belajar 15

1. Flip-flop J-K

Kelemahan flip-flop S-R adalah munculnya output yang tidak dapat

didefinisikan ketika input S dan R tinggi untuk jenis NOR dan rendah untuk

jenis NAND.Untuk menanggulanginya muncul keadaan tersebut,maka

dikembangkan flip-flop J-K, flip-flop J-K dibangun untuk mengantisipasi

keadaan terlarang pada flip-flop S-R, dan rangaian ditunjukan pada gambar di

bawah ini.

Gambar 1.1 Logic diagram dan logic simbol IC 7476

Konfigurasi diatas telah dapat menghilangkan keadaan terlarang yang terjadi

pada flip-flop S-R.Penggunaan flip-flop J-K dapat menimbulkan masalah

apabila sinyal input J dan K diberikan bersamaan dengan sinyal clock

pemicu.Misal flip-flop J-K dioperasikan dalam keadaan set,sehingga input

diberikan keadaan tinggi ( J = 1) dan inpu K diberikan keadaan rendah

(K=0).Perlu dikemukakan terlebih dahulu bahwa pada umumnya sinyal-sinyal

pemicu flip-flop termasuk sinyal input ketika diumpankan ke input-input flip-

flop tidak langsung bernilai tinggi,namun memerlukan waktu tertentu atau

mengalami penundaan dalam mencapai keadaan stabil.

Page 2: A. Judul : FLIP-FLOP JK B. C. 1. - elektro.um.ac.idelektro.um.ac.id/wp-content/uploads/2016/04/Sistem-Digital-JK.pdf · dikembangkan flip-flop J-K, flip-flop J-K dibangun untuk mengantisipasi

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2. KARAKTERISTIK IC TTL

+5V

4KΩ

Ke Rangkaian selanjutnya

Ke Rangkaian selanjutnya

I

E

B

C

Gambar 1.3 Rangkaian ekivalen input IC TTL ( Input = 0 )

Bila masukkan IC TTL dihubungkan ground maka ada beda potensial

antara basis dan emitter, sehingga arus mengalir menuju emitter, tidak ada arus

yang mengalir menuju colector. Input IC TTL sama dengan nol.

+5V

4KΩ

+5V

I

Ke Rangkaian selanjutnya

Ke Rangkaian selanjutnyaE

B

C

Gambar 1.4 Rangkaian ekivalen input IC TTL ( Input = 1 )

Bila masukan IC TTL dihubungkan dengan +5V, maka tidak ada beda

potensial antara basis dan emiter Tr1. Sehingga arus mengalir menuju colector

Tr1 dan menuju basis Tr2, tidak ada arus yang mengalir menuju emiter. Input IC

TTL sama dengan 1.

Page 3: A. Judul : FLIP-FLOP JK B. C. 1. - elektro.um.ac.idelektro.um.ac.id/wp-content/uploads/2016/04/Sistem-Digital-JK.pdf · dikembangkan flip-flop J-K, flip-flop J-K dibangun untuk mengantisipasi

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+5V

4KΩ

Mengambang

I

Ke Rangkaian selanjutnyaE

B

C

Ke Rangkaian selanjutnya

Gambar 1.5 Rangkaian ekivalen input IC TTL ( Input = 1 )

Bila masukan IC TTL tidak dihubungkan dengan +5V atau ground (

mengambang ), maka tidak ada beda potensial antara basis dan emiter Tr1.

Sehingga arus mengalir menuju colector Tr1 dan menuju basis Tr2, tidak ada arus

yang mengalir menuju emiter. Input IC TTL sama dengan 1.

D. Lembar Praktikum

1. Alat dan Bahan

Modul trainer Flip-Flop J-K 1 buah

Catu daya 1 buah

Saklar input logika 1 buah

Kabel jumper kuning 4 buah

Kabel jumper merah 2 buah

2. Kesehatan dan Keselamatan kerja

(a) Periksalah komponen modul trainer sebelum digunakan.

(b) Pelajari dan pahami petunjuk praktikum pada lembar kegiatan

praktikum.

(c) Pastikan tegangan keluaran catu daya sesuai yang dibutuhkan.

(d) Sebelum catu daya dihidupkan hubungi dosen pendamping untuk

mengecek kebenaran rangkaian.

(e) Yakinkan tempat anda aman dari sengatan listrik.

(f) Hati-hati dalam penggunaan peralatan praktikum !

Page 4: A. Judul : FLIP-FLOP JK B. C. 1. - elektro.um.ac.idelektro.um.ac.id/wp-content/uploads/2016/04/Sistem-Digital-JK.pdf · dikembangkan flip-flop J-K, flip-flop J-K dibangun untuk mengantisipasi

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3. Langkah percobaan 2

a) Perhatikan gambar 1.2 lalu cermati konektor yang ada pada modul

Flip-Flop J-K.

10K

47pf

J

K

Q

Q

SD

CD

CLK1

4

16

15

14

2

3

7476

VCC +5V

330 Ω

Y1

330 Ω

Gambar 1.2 Rangkaian percobaan Flip-Flop J-K

b) Berilah modul Flip-Flop J-K tegangan sebesar 5VDC dengan cara

menghubungkan vcc dan ground power supply ke vcc dan ground

modul Flip-Flop J-K menggunakan kabel penghubung yang sudah

disediakan.

c) Berilah saklar input logika dengan tegangan 5VDC dengan

mnghubungkan ground dan vcc power supply pada pin paling atas

sesuai gambar.

d) Hubungkan kaki-kaki input J, K, SD, CD dengan Vcc atau ground

sesuai dengan kombinasi pada tabel 1.1.

e) Hubungkan kaki-kaki output Q dan Q dengan LED seperti pada

gambar 1.3.

f) Catat kondisi nyala lampu led yang terhubung dengan Q dan Q pada

tabel 1.1

Page 5: A. Judul : FLIP-FLOP JK B. C. 1. - elektro.um.ac.idelektro.um.ac.id/wp-content/uploads/2016/04/Sistem-Digital-JK.pdf · dikembangkan flip-flop J-K, flip-flop J-K dibangun untuk mengantisipasi

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+ 5V

BOOST CONVERTERFF-JK DAN FF-D

10K

10K

+ 5V

+ 5V

GND

GND

47pf

47pf

220

330

330

220

J

K

Q

Q

SD

CD

CLK1

4

16

15

14

2

3

D Q

Q

SD

CD

CLK3

2 5

6

4

1

FF-D

FF-JK

+ 5V

7474

7476

Gambar 1.3 modul Flip-Flop J-K

Page 6: A. Judul : FLIP-FLOP JK B. C. 1. - elektro.um.ac.idelektro.um.ac.id/wp-content/uploads/2016/04/Sistem-Digital-JK.pdf · dikembangkan flip-flop J-K, flip-flop J-K dibangun untuk mengantisipasi

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E. HASIL PRAKTIKUM

Tabel 1.1 Tabel Hasil Percobaan

INPUT OUTPUT

CLOCK SD CD J K Q Q NOT

0 1 X X

1 0 X X

0 0 X X

1 1 1 1

1 1 0 1

1 1 1 0

1 1 0 0

Keterangan :

Led menyala = 1 Logika 1 = vcc (5V ) X= tidak di hiraukan

Led mati = 0 Logika 0 = ground

Page 7: A. Judul : FLIP-FLOP JK B. C. 1. - elektro.um.ac.idelektro.um.ac.id/wp-content/uploads/2016/04/Sistem-Digital-JK.pdf · dikembangkan flip-flop J-K, flip-flop J-K dibangun untuk mengantisipasi

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F. GAMBAR PRAKTIKUM

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Analisa

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G. GAMBAR SIMULASI SOFTWARE (PRAKTIKUM)

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Analisa

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4. Tugas :

a. Bagaimana cara membuat keadaan set dan reset pada flip-flop J-K ?

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b. Buat rangkaian Flip-flop menggunakan gerbang NAND 3 masukan dan

gerbang NAND 2 masukan (simulasikan) !

Tabel Kebenaran

Clock J K Q Qnot

1 0 0

1 0 1

1 1 0

1 1 1

Gambar Simulasi Software (TUGAS)

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Analisa

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Daftar Pustaka

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