organi sasi komputer dosen pembimbing : khairil anwar, st smik-lpwn hamzanwadi pancor

Organisasi KomputerDosen Pembimbing : Khairil Anwar, ST

SMIK-LPWN HAMZANWADI PANCOR

Materi 3Bus-Bus Sistem

Konsep Program

Sistem hardware tidak fleksibelTujuan umum hardware untuk melakukan tugas-tugas yang berbeda, dengan jalan memberikan koresksi sinyal kontrolDengan mengubah hubungan (re-wiring),berarti memberikan set sinyal kontrol baru

Apa itu program?

Suatu urutan langkah-langkah kerjaUntuk tiap langkah, suatu operasi aritmatik atau logika dilakukanUntuk tiap operasi, dibutuhkan pengaturan sinyal kontrol yang berbeda

Fungsi Unit Kontrol

Biasanya setiap operasi mempunyai kode yang unik

Misal ADD, MOVE

Suatu bagian hardware menerima kode dan mengirimkan sinyal kontrol

We have a computer!

Komponen - komponenUnit Kontrol dan ALU merupakan bagian yang terdapat dalam CPU (Central Processing Unit)Data and instruksi perlu dimasukkan ke dalam sistem untuk mendapatkan suatu keluaran

Input/outputMedia penyimpanan sementara (temporary storage) kode and hasil proses diperlukan

Memori utama

Komponen Komputer :Top Level View

Putaran instruksi

Dua langkah:FetchExecute

Putaran Fetch

Program Counter (PC) menyimpan alamat instruksi berikutnya untuk di fetchProsessor mem-fetch-kan instruksi dari lokasi memori yang ditunjuk oleh PCPeningkatan PCInstruksi dikirim ke Instruction Register (IR)Prosessor menginterpretasikan instruksi dan melakukan aksi yang diperlukan

Putaran EksekusiProcessor-memory

Data ditransfer antara CPU dan memori utama

Processor I/OData ditransfer antara CPU dan modul I/O

Data processingBeberapa operasi aritmatik dan logika terhadap data

ControlMengatur urutan-urutan operasiMisalnya jump

Kombinasi proses di atas

Contoh Eksekusi Program

Putaran Instruksi - State Diagram

InterupsiMekanisme oleh modul-modul lainnya (mis. I/O) untuk mengubah urutan normal proses yang berlangsungProgram

Misal : overflow, division by zero

TimerDihasilkan oleh internal processor timerDigunakan dalam pre-emptive multi-tasking

I/ODari pengontrol I/O

Hardware failureMisalnya bit paritas memori error

Program Flow Control

Lingkaran InterruptDitambahkan ke dalam putaran instruksiProsessor mencek adanya interrupt

Diindikasikan oleh suatu interrupt signalJika tidak ada interrupt, fetch instruksi berikutnyaJika interrupt ditunda:

Sedang mengksekusi program Save contextSeting PC untuk memulai alamat interrupt handler routineProses interruptKembalikan context dan lanjtkan program yang di interrupt

Putaran Instruction (dengan Interrupts) - State Diagram

Multiple InterruptsDisable interrupts

Processor will ignore further interrupts whilst processing one interruptInterrupts remain pending and are checked after first interrupt has been processedInterrupts handled in sequence as they occur

Define prioritiesLow priority interrupts can be interrupted by higher priority interruptsWhen higher priority interrupt has been processed, processor returns to previous interrupt

Multiple Interrupts - Sequential

Multiple Interrupts - Nested

Connecting

All the units must be connectedDifferent type of connection for different type of unit

MemoryInput/OutputCPU

Memory Connection

Receives and sends dataReceives addresses (of locations)Receives control signals

ReadWriteTiming

Input/Output Connection(1)

Similar to memory from computer’s viewpointOutput

Receive data from computerSend data to peripheral

InputReceive data from peripheralSend data to computer

Input/Output Connection(2)

Receive control signals from computerSend control signals to peripherals

e.g. spin disk

Receive addresses from computere.g. port number to identify peripheral

Send interrupt signals (control)

CPU Connection

Reads instruction and dataWrites out data (after processing)Sends control signals to other unitsReceives (& acts on) interrupts

Buses

There are a number of possible interconnection systemsSingle and multiple BUS structures are most commone.g. Control/Address/Data bus (PC)e.g. Unibus (DEC-PDP)

What is a Bus?

A communication pathway connecting two or more devicesUsually broadcast Often grouped

A number of channels in one buse.g. 32 bit data bus is 32 separate single bit channels

Power lines may not be shown

Data Bus

Carries dataRemember that there is no difference between “data” and “instruction” at this level

Width is a key determinant of performance

8, 16, 32, 64 bit

Address bus

Identify the source or destination of datae.g. CPU needs to read an instruction (data) from a given location in memoryBus width determines maximum memory capacity of system

e.g. 8080 has 16 bit address bus giving 64k address space

Control Bus

Control and timing informationMemory read/write signalInterrupt requestClock signals

Bus Interconnection Scheme

Big and Yellow?

What do buses look like?Parallel lines on circuit boardsRibbon cablesStrip connectors on mother boards• e.g. PCI

Sets of wires

Single Bus Problems

Lots of devices on one bus leads to:Propagation delays• Long data paths mean that co-ordination of

bus use can adversely affect performance• If aggregate data transfer approaches bus

capacity

Most systems use multiple buses to overcome these problems

Traditional (ISA)(with cache)

High Performance Bus

Bus Types

DedicatedSeparate data & address lines

MultiplexedShared linesAddress valid or data valid control lineAdvantage - fewer linesDisadvantages

• More complex control• Ultimate performance

Bus Arbitration

More than one module controlling the buse.g. CPU and DMA controllerOnly one module may control bus at one timeArbitration may be centralised or distributed

Centralised Arbitration

Single hardware device controlling bus access

Bus ControllerArbiter

May be part of CPU or separate

Distributed Arbitration

Each module may claim the busControl logic on all modules

Timing

Co-ordination of events on busSynchronous

Events determined by clock signalsControl Bus includes clock lineA single 1-0 is a bus cycleAll devices can read clock lineUsually sync on leading edgeUsually a single cycle for an event

Synchronous Timing Diagram

Asynchronous Timing Diagram

PCI Bus

Peripheral Component InterconnectionIntel released to public domain32 or 64 bit50 lines

PCI Bus Lines (required)Systems lines

Including clock and reset

Address & Data32 time mux lines for address/dataInterrupt & validate lines

Interface ControlArbitration

Not sharedDirect connection to PCI bus arbiter

Error lines

PCI Bus Lines (Optional)Interrupt lines

Not shared

Cache support64-bit Bus Extension

Additional 32 linesTime multiplexed2 lines to enable devices to agree to use 64-bit transfer

JTAG/Boundary ScanFor testing procedures

PCI Commands

Transaction between initiator (master) and targetMaster claims busDetermine type of transaction

e.g. I/O read/write

Address phaseOne or more data phases

PCI Read Timing Diagram

PCI Bus Arbitration

Foreground Reading

Stallings, chapter 3 (all of it)www.pcguide.com/ref/mbsys/buses/

In fact, read the whole site!www.pcguide.com/