organi sasi komputer dosen pembimbing : khairil anwar, st smik-lpwn hamzanwadi pancor

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Organisasi Komputer Dosen Pembimbing : Khairil Anwar, ST SMIK-LPWN HAMZANWADI PANCOR Materi 3 Bus-Bus Sistem

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Organi sasi Komputer Dosen Pembimbing : Khairil Anwar, ST SMIK-LPWN HAMZANWADI PANCOR. Materi 3 Bus-Bus Sistem. Konsep Program. Sistem hardware tidak fleksibel Tujuan umum hardware untuk melakukan tugas-tugas yang berbeda , dengan jalan memberikan koresksi sinyal kontrol - PowerPoint PPT Presentation

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Page 1: Organi sasi Komputer Dosen Pembimbing : Khairil Anwar, ST SMIK-LPWN HAMZANWADI PANCOR

Organisasi KomputerDosen Pembimbing : Khairil Anwar, ST

SMIK-LPWN HAMZANWADI PANCOR

Materi 3Bus-Bus Sistem

Page 2: Organi sasi Komputer Dosen Pembimbing : Khairil Anwar, ST SMIK-LPWN HAMZANWADI PANCOR

Konsep ProgramSistem hardware tidak fleksibelTujuan umum hardware untuk melakukan tugas-tugas yang berbeda, dengan jalan memberikan koresksi sinyal kontrolDengan mengubah hubungan (re-wiring),berarti memberikan set sinyal kontrol baru

Page 3: Organi sasi Komputer Dosen Pembimbing : Khairil Anwar, ST SMIK-LPWN HAMZANWADI PANCOR

Apa itu program?Suatu urutan langkah-langkah kerjaUntuk tiap langkah, suatu operasi aritmatik atau logika dilakukanUntuk tiap operasi, dibutuhkan pengaturan sinyal kontrol yang berbeda

Page 4: Organi sasi Komputer Dosen Pembimbing : Khairil Anwar, ST SMIK-LPWN HAMZANWADI PANCOR

Fungsi Unit KontrolBiasanya setiap operasi mempunyai kode yang unik

Misal ADD, MOVESuatu bagian hardware menerima kode dan mengirimkan sinyal kontrol

We have a computer!

Page 5: Organi sasi Komputer Dosen Pembimbing : Khairil Anwar, ST SMIK-LPWN HAMZANWADI PANCOR

Komponen - komponenUnit Kontrol dan ALU merupakan bagian yang terdapat dalam CPU (Central Processing Unit)Data and instruksi perlu dimasukkan ke dalam sistem untuk mendapatkan suatu keluaran

Input/outputMedia penyimpanan sementara (temporary storage) kode and hasil proses diperlukan

Memori utama

Page 6: Organi sasi Komputer Dosen Pembimbing : Khairil Anwar, ST SMIK-LPWN HAMZANWADI PANCOR

Komponen Komputer :Top Level View

Page 7: Organi sasi Komputer Dosen Pembimbing : Khairil Anwar, ST SMIK-LPWN HAMZANWADI PANCOR

Putaran instruksiDua langkah:

FetchExecute

Page 8: Organi sasi Komputer Dosen Pembimbing : Khairil Anwar, ST SMIK-LPWN HAMZANWADI PANCOR

Putaran FetchProgram Counter (PC) menyimpan alamat instruksi berikutnya untuk di fetchProsessor mem-fetch-kan instruksi dari lokasi memori yang ditunjuk oleh PCPeningkatan PCInstruksi dikirim ke Instruction Register (IR)Prosessor menginterpretasikan instruksi dan melakukan aksi yang diperlukan

Page 9: Organi sasi Komputer Dosen Pembimbing : Khairil Anwar, ST SMIK-LPWN HAMZANWADI PANCOR

Putaran EksekusiProcessor-memory

Data ditransfer antara CPU dan memori utamaProcessor I/O

Data ditransfer antara CPU dan modul I/O Data processing

Beberapa operasi aritmatik dan logika terhadap data

ControlMengatur urutan-urutan operasiMisalnya jump

Kombinasi proses di atas

Page 10: Organi sasi Komputer Dosen Pembimbing : Khairil Anwar, ST SMIK-LPWN HAMZANWADI PANCOR

Contoh Eksekusi Program

Page 11: Organi sasi Komputer Dosen Pembimbing : Khairil Anwar, ST SMIK-LPWN HAMZANWADI PANCOR

Putaran Instruksi - State Diagram

Page 12: Organi sasi Komputer Dosen Pembimbing : Khairil Anwar, ST SMIK-LPWN HAMZANWADI PANCOR

InterupsiMekanisme oleh modul-modul lainnya (mis. I/O) untuk mengubah urutan normal proses yang berlangsungProgram

Misal : overflow, division by zeroTimer

Dihasilkan oleh internal processor timerDigunakan dalam pre-emptive multi-tasking

I/ODari pengontrol I/O

Hardware failureMisalnya bit paritas memori error

Page 13: Organi sasi Komputer Dosen Pembimbing : Khairil Anwar, ST SMIK-LPWN HAMZANWADI PANCOR

Program Flow Control

Page 14: Organi sasi Komputer Dosen Pembimbing : Khairil Anwar, ST SMIK-LPWN HAMZANWADI PANCOR

Lingkaran InterruptDitambahkan ke dalam putaran instruksiProsessor mencek adanya interrupt

Diindikasikan oleh suatu interrupt signalJika tidak ada interrupt, fetch instruksi berikutnyaJika interrupt ditunda:

Sedang mengksekusi program Save contextSeting PC untuk memulai alamat interrupt handler routineProses interruptKembalikan context dan lanjtkan program yang di interrupt

Page 15: Organi sasi Komputer Dosen Pembimbing : Khairil Anwar, ST SMIK-LPWN HAMZANWADI PANCOR

Putaran Instruction (dengan Interrupts) - State Diagram

Page 16: Organi sasi Komputer Dosen Pembimbing : Khairil Anwar, ST SMIK-LPWN HAMZANWADI PANCOR

Multiple InterruptsDisable interrupts

Processor will ignore further interrupts whilst processing one interruptInterrupts remain pending and are checked after first interrupt has been processedInterrupts handled in sequence as they occur

Define prioritiesLow priority interrupts can be interrupted by higher priority interruptsWhen higher priority interrupt has been processed, processor returns to previous interrupt

Page 17: Organi sasi Komputer Dosen Pembimbing : Khairil Anwar, ST SMIK-LPWN HAMZANWADI PANCOR

Multiple Interrupts - Sequential

Page 18: Organi sasi Komputer Dosen Pembimbing : Khairil Anwar, ST SMIK-LPWN HAMZANWADI PANCOR

Multiple Interrupts - Nested

Page 19: Organi sasi Komputer Dosen Pembimbing : Khairil Anwar, ST SMIK-LPWN HAMZANWADI PANCOR

ConnectingAll the units must be connectedDifferent type of connection for different type of unit

MemoryInput/OutputCPU

Page 20: Organi sasi Komputer Dosen Pembimbing : Khairil Anwar, ST SMIK-LPWN HAMZANWADI PANCOR

Memory ConnectionReceives and sends dataReceives addresses (of locations)Receives control signals

ReadWriteTiming

Page 21: Organi sasi Komputer Dosen Pembimbing : Khairil Anwar, ST SMIK-LPWN HAMZANWADI PANCOR

Input/Output Connection(1)Similar to memory from computer’s viewpointOutput

Receive data from computerSend data to peripheral

InputReceive data from peripheralSend data to computer

Page 22: Organi sasi Komputer Dosen Pembimbing : Khairil Anwar, ST SMIK-LPWN HAMZANWADI PANCOR

Input/Output Connection(2)Receive control signals from computerSend control signals to peripherals

e.g. spin diskReceive addresses from computer

e.g. port number to identify peripheralSend interrupt signals (control)

Page 23: Organi sasi Komputer Dosen Pembimbing : Khairil Anwar, ST SMIK-LPWN HAMZANWADI PANCOR

CPU ConnectionReads instruction and dataWrites out data (after processing)Sends control signals to other unitsReceives (& acts on) interrupts

Page 24: Organi sasi Komputer Dosen Pembimbing : Khairil Anwar, ST SMIK-LPWN HAMZANWADI PANCOR

BusesThere are a number of possible interconnection systemsSingle and multiple BUS structures are most commone.g. Control/Address/Data bus (PC)e.g. Unibus (DEC-PDP)

Page 25: Organi sasi Komputer Dosen Pembimbing : Khairil Anwar, ST SMIK-LPWN HAMZANWADI PANCOR

What is a Bus?A communication pathway connecting two or more devicesUsually broadcast Often grouped

A number of channels in one buse.g. 32 bit data bus is 32 separate single bit channels

Power lines may not be shown

Page 26: Organi sasi Komputer Dosen Pembimbing : Khairil Anwar, ST SMIK-LPWN HAMZANWADI PANCOR

Data BusCarries data

Remember that there is no difference between “data” and “instruction” at this level

Width is a key determinant of performance

8, 16, 32, 64 bit

Page 27: Organi sasi Komputer Dosen Pembimbing : Khairil Anwar, ST SMIK-LPWN HAMZANWADI PANCOR

Address busIdentify the source or destination of datae.g. CPU needs to read an instruction (data) from a given location in memoryBus width determines maximum memory capacity of system

e.g. 8080 has 16 bit address bus giving 64k address space

Page 28: Organi sasi Komputer Dosen Pembimbing : Khairil Anwar, ST SMIK-LPWN HAMZANWADI PANCOR

Control BusControl and timing information

Memory read/write signalInterrupt requestClock signals

Page 29: Organi sasi Komputer Dosen Pembimbing : Khairil Anwar, ST SMIK-LPWN HAMZANWADI PANCOR

Bus Interconnection Scheme

Page 30: Organi sasi Komputer Dosen Pembimbing : Khairil Anwar, ST SMIK-LPWN HAMZANWADI PANCOR

Big and Yellow?What do buses look like?

Parallel lines on circuit boardsRibbon cablesStrip connectors on mother boards• e.g. PCI

Sets of wires

Page 31: Organi sasi Komputer Dosen Pembimbing : Khairil Anwar, ST SMIK-LPWN HAMZANWADI PANCOR

Single Bus ProblemsLots of devices on one bus leads to:

Propagation delays• Long data paths mean that co-ordination of

bus use can adversely affect performance• If aggregate data transfer approaches bus

capacityMost systems use multiple buses to overcome these problems

Page 32: Organi sasi Komputer Dosen Pembimbing : Khairil Anwar, ST SMIK-LPWN HAMZANWADI PANCOR

Traditional (ISA)(with cache)

Page 33: Organi sasi Komputer Dosen Pembimbing : Khairil Anwar, ST SMIK-LPWN HAMZANWADI PANCOR

High Performance Bus

Page 34: Organi sasi Komputer Dosen Pembimbing : Khairil Anwar, ST SMIK-LPWN HAMZANWADI PANCOR

Bus TypesDedicated

Separate data & address linesMultiplexed

Shared linesAddress valid or data valid control lineAdvantage - fewer linesDisadvantages

• More complex control• Ultimate performance

Page 35: Organi sasi Komputer Dosen Pembimbing : Khairil Anwar, ST SMIK-LPWN HAMZANWADI PANCOR

Bus ArbitrationMore than one module controlling the buse.g. CPU and DMA controllerOnly one module may control bus at one timeArbitration may be centralised or distributed

Page 36: Organi sasi Komputer Dosen Pembimbing : Khairil Anwar, ST SMIK-LPWN HAMZANWADI PANCOR

Centralised ArbitrationSingle hardware device controlling bus access

Bus ControllerArbiter

May be part of CPU or separate

Page 37: Organi sasi Komputer Dosen Pembimbing : Khairil Anwar, ST SMIK-LPWN HAMZANWADI PANCOR

Distributed ArbitrationEach module may claim the busControl logic on all modules

Page 38: Organi sasi Komputer Dosen Pembimbing : Khairil Anwar, ST SMIK-LPWN HAMZANWADI PANCOR

TimingCo-ordination of events on busSynchronous

Events determined by clock signalsControl Bus includes clock lineA single 1-0 is a bus cycleAll devices can read clock lineUsually sync on leading edgeUsually a single cycle for an event

Page 39: Organi sasi Komputer Dosen Pembimbing : Khairil Anwar, ST SMIK-LPWN HAMZANWADI PANCOR

Synchronous Timing Diagram

Page 40: Organi sasi Komputer Dosen Pembimbing : Khairil Anwar, ST SMIK-LPWN HAMZANWADI PANCOR

Asynchronous Timing Diagram

Page 41: Organi sasi Komputer Dosen Pembimbing : Khairil Anwar, ST SMIK-LPWN HAMZANWADI PANCOR

PCI BusPeripheral Component InterconnectionIntel released to public domain32 or 64 bit50 lines

Page 42: Organi sasi Komputer Dosen Pembimbing : Khairil Anwar, ST SMIK-LPWN HAMZANWADI PANCOR

PCI Bus Lines (required)Systems lines

Including clock and resetAddress & Data

32 time mux lines for address/dataInterrupt & validate lines

Interface ControlArbitration

Not sharedDirect connection to PCI bus arbiter

Error lines

Page 43: Organi sasi Komputer Dosen Pembimbing : Khairil Anwar, ST SMIK-LPWN HAMZANWADI PANCOR

PCI Bus Lines (Optional)Interrupt lines

Not sharedCache support64-bit Bus Extension

Additional 32 linesTime multiplexed2 lines to enable devices to agree to use 64-bit transfer

JTAG/Boundary ScanFor testing procedures

Page 44: Organi sasi Komputer Dosen Pembimbing : Khairil Anwar, ST SMIK-LPWN HAMZANWADI PANCOR

PCI CommandsTransaction between initiator (master) and targetMaster claims busDetermine type of transaction

e.g. I/O read/writeAddress phaseOne or more data phases

Page 45: Organi sasi Komputer Dosen Pembimbing : Khairil Anwar, ST SMIK-LPWN HAMZANWADI PANCOR

PCI Read Timing Diagram

Page 46: Organi sasi Komputer Dosen Pembimbing : Khairil Anwar, ST SMIK-LPWN HAMZANWADI PANCOR

PCI Bus Arbitration

Page 47: Organi sasi Komputer Dosen Pembimbing : Khairil Anwar, ST SMIK-LPWN HAMZANWADI PANCOR

Foreground ReadingStallings, chapter 3 (all of it)www.pcguide.com/ref/mbsys/buses/

In fact, read the whole site!www.pcguide.com/