loop dan fifo

8/10/2019 Loop Dan Fifo

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LOOPS

STATEMENT


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Pengertian

Loop statements digunakan untuk operasi yang

berulang-ulang

Terdiri dari statement : for loops atau while loops

Statement forakan mengeksekusi sampai nomor

tertentu secara berulang, (controlling number)

Statement whileakan mengeksekusi perintah

terus selama kondisi disyaratkan masih benar.


3/19


4/19

While for statement

reg_array : process (rst, clk)

variable i : integer := 0;

begin

if rst = 1 thenwhile i < 7 loop

fifo(i) 0);

i := i + 1;

end loop;

..


5/19

Skip condition

Misalnya jika reset diaktifkan semua array fifo bernilai 0 kecualififo (4) register.

reg_array : process(rst , clk)

begin

ifrst = 1 then

fori in7 downto 0 loop

ifi = 4 then

next;

else

fifo(i) 0);end if;

endloop;

.


6/19

In while loop statementreg_array : process(rst, clk)

variable i : integer;

begin

I := 0;

ifrst = 1 then

whilei < 8 loop

if i = 4then

next;

else

fifo(i) 0);

i := i + 1;end if;

end loop;

..


7/19

Exit the loop statement

reg_array: process(rst, clk)

begin

ifrst = 1 then

loop1 : fori indeep downto0 loop

if i > 20 then

exit loop1;

else

fifo(i) 0);end if;

endloop;


8/19

Alternative statement

Reg_array: process(rst,clk)

begin

ifrst = 1 then

loop1: fori indeep downto0 loop

exitloop1 wheni > 20;

fifo(i) 0);

end loop;


9/19

Array bit

ifwr = 1 then

fori in7 downto0 loop

ifen(i) = 1 then

fifo(i)


10/19

Mendisain FIFO

-------------------------------------------------------------------------------

--

-- Title : fifo8x9

-- Design : fifo

-- Author :

-- Company :

--

-------------------------------------------------------------------------------

--

-- File : d:\vhdl\my_design\fifo\fifo\src\fifo.vhd

-- Generated : Sun Oct 19 17:39:03 2014-- From : interface description file

-- By : Itf2Vhdl ver. 1.22

--


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-------------------------------------------------------------------------------

--

-- Description :

--

-------------------------------------------------------------------------------

--{{ Section below this comment is automatically maintained -- and may be overwritten

--{entity {fifo8x9} architecture {archfifo8x9}}

library IEEE;

use IEEE.std_logic_arith.all;

use IEEE.std_logic_unsigned.all; use IEEE.STD_LOGIC_1164.all;

use IEEE.STD_LOGIC_ARITH.all;

use IEEE.STD_LOGIC_UNSIGNED.all;


12/19

entity fifo8x9 is

port( clk : in STD_LOGIC;

rst : in STD_LOGIC;

rd : in STD_LOGIC;

wr : in STD_LOGIC;

rdinc : in STD_LOGIC; wrinc : in STD_LOGIC;

rdptrclr : in STD_LOGIC;

wrptrclr : in STD_LOGIC;

data_in : in STD_LOGIC_VECTOR(8 downto 0);

data_out : out STD_LOGIC_VECTOR(8 downto 0) );

end fifo8x9;

--}} End of automatically maintained section


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architecture archfifo8x9 of fifo8x9 is

type fifo_array is array(7 downto 0) of

std_logic_vector(8 downto 0);

signal fifo : fifo_array;

signal wrptr, rdptr: std_logic_vector(2 downto 0);

signal en : std_logic_vector(7 downto 0);

signal dmuxout : std_logic_vector(8 downto 0);


14/19

begin

---- fifo register array :

reg_array: process (rst, clk) begin

if rst = '1' then

for i in 7 downto 0 loop

fifo(i) '0');

end loop;

elsif (clk'event and clk = '1') then

if wr = '1' then for i in 7 downto 0 loop

if en(i) = '1' then

fifo(i)


15/19

------ read pointer

read_count: process (rst, clk) begin

if rst = '1' then

rdptr '0');


if rdptrclr = '1' then

rdptr '0');

elsif rdinc = '1' then

rdptr


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------ write pointer

write_count: process (rst, clk) begin

if rst = '1' then

wrptr '0');


if wrptrclr = '1' then

wrptr '0');

elsif wrinc = '1' then

wrptr


17/19

------ 8 : 1 output data mux

with rdptr select

dmuxout


18/19

------- fifo register selector decoder

with wrptr select

en


19/19

------- three state control of output three_state: process (rd, dmuxout)

begin

if rd = '1' then

data_out

loop dan fifo

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