iki10230 pengantar organisasi komputer bab 4.2: dma & bus

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IKI10230Pengantar Organisasi Komputer

Bab 4.2: DMA & Bus

26 Maret 2003

Bobby Nazief (nazief@cs.ui.ac.id)Qonita Shahab (niet@cs.ui.ac.id)

bahan kuliah: http://www.cs.ui.ac.id/kuliah/iki10230/

Sumber:1. Hamacher. Computer Organization, ed-5.2. Materi kuliah CS152/1997, UCB.

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DMA

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Improving Data Transfer Performance

° Thus far: OS give commands to I/O, I/O device notify OS when the I/O device completed operation or an error

° What about data transfer to I/O device?• Processor busy doing loads/stores between memory and I/O Data

Register:

Wait:sbis DiskControl,1 ; is Disk ready?rjmp Wait ; noin r0,DiskData ; get bytest X+,r0 ; store itdec r16 ; done?bne Wait ; not yet

° Ideal: specify the block of memory to be transferred, be notified on completion?

• Direct Memory Access (DMA) : a simple computer transfers a block of data to/from memory and I/O without involving the processor, interrupting upon done

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Delegating I/O Responsibility from the CPU: DMA

° Direct Memory Access (DMA):• External to the CPU

• Act as a maser on the bus

• Transfer blocks of data to or from memory without CPU intervention

CPU

IOC

device

Memory DMAC

CPU sends a starting address, direction, and length count to DMAC. Then issues "start".

DMAC provides handshakesignals for PeripheralController, and MemoryAddresses and handshakesignals for Memory.

Issue:• Who controls the BUS?

(CPU or DMAC may do so)

• How?

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Arbitration: Obtaining Access to the Bus

Bus Arbitration

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Multiple Potential Bus Masters: the Need for Arbitration

° Bus arbitration scheme:• A bus master wanting to use the bus asserts the bus request

• A bus master cannot use the bus until its request is granted

• A bus master must signal to the arbiter after finish using the bus

° Bus arbitration schemes usually try to balance two factors:

• Bus priority: the highest priority device should be serviced first

• Fairness: Even the lowest priority device should never be completely locked out from the bus

° Bus arbitration schemes can be divided into four broad classes:

• Daisy chain arbitration: single device with all request lines.

• Centralized, parallel arbitration: see next-next slide

• Distributed arbitration by self-selection: each device wanting the bus places a code indicating its identity on the bus.

• Distributed arbitration by collision detection: Ethernet uses this.

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The Daisy Chain Bus Arbitrations Scheme

° Advantage: simple

° Disadvantages:• Cannot assure fairness:

A low-priority device may be locked out indefinitely

• The use of the daisy chain grant signal also limits the bus speed

BusArbiter

Device 1HighestPriority

Device NLowestPriority

Device 2

Grant Grant Grant

Release

Request

wired-OR

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Centralized Parallel Arbitration

° Used in essentially all processor-memory busses and in high-speed I/O busses

BusArbiter

Device 1 Device NDevice 2

Grant Req

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Types of Buses

More on BUS

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A Computer System with One Bus: Backplane Bus

° A single bus (the backplane bus) is used for:• Processor to memory communication

• Communication between I/O devices and memory

° Advantages: Simple and low cost

° Disadvantages: slow and the bus can become a major bottleneck

° Example: IBM PC - AT

Processor Memory

I/O Devices

Backplane Bus

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A Two-Bus System

° I/O buses tap into the processor-memory bus via bus adaptors:

• Processor-memory bus: mainly for processor-memory traffic

• I/O buses: provide expansion slots for I/O devices

° Apple Macintosh-II• NuBus: Processor, memory, and a few selected I/O devices

• SCCI Bus: the rest of the I/O devices

Processor Memory

I/OBus

Processor Memory Bus

BusAdaptor

BusAdaptor

BusAdaptor

I/OBus

I/OBus

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A Three-Bus System

° A small number of backplane buses tap into the processor-memory bus

• Processor-memory bus is used for processor memory traffic

• I/O buses are connected to the backplane bus

° Advantage: loading on the processor bus is greatly reduced

Processor Memory

Processor Memory Bus

BusAdaptor

BusAdaptor

BusAdaptor

I/O Bus (e.g., SCSI)Backplane Bus

(e.g., PCI) I/O Bus

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What defines a bus?

Bunch of Wires

Physical / Mechanical Characterisics – the connectors

Electrical Specification

Timing and Signaling Specification

Transaction Protocol

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Synchronous and Asynchronous Bus

° Synchronous Bus:• Includes a clock in the control lines

• A fixed protocol for communication that is relative to the clock

• Advantage: involves very little logic and can run very fast

• Disadvantages:

- Every device on the bus must run at the same clock rate

- To avoid clock skew, they cannot be long if they are fast

° Asynchronous Bus:• It is not clocked

• It can accommodate a wide range of devices

• It can be lengthened without worrying about clock skew

• It requires a handshaking protocol

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Simplest bus paradigm

° All agents operate syncronously

° All can source / sink data at same rate

° => simple protocol• just manage the source and target

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Simple Synchronous Protocol

° Even memory busses are more complex than this• memory (slave) may take time to respond

• it need to control data rate

BReq

BG

Cmd+AddrR/WAddress

Data1 Data2Data

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Typical Synchronous Protocol

° Slave indicates when it is prepared for data xfer

° Actual transfer goes at bus rate

BReq

BG

Cmd+AddrR/WAddress

Data1 Data2Data Data1

Wait

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Asynchronous Handshake

Address

Data

Write

Req

Ack

Master Asserts Address

Master Asserts Data

Next Address

Write Transaction

t0 t1 t2 t3 t4 t5° t0 : Master has obtained control and asserts address, direction, data

° Waits a specified amount of time for slaves to decode target

° t1: Master asserts request line

° t2: Slave asserts ack, indicating data received

° t3: Master releases req

° t4: Slave releases ack

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Read Transaction

Address

Data

Read

Req

Ack

Master Asserts Address Next Address

t0 t1 t2 t3 t4 t5° t0 : Master has obtained control and asserts address, direction, data

° Waits a specified amount of time for slaves to decode target\

° t1: Master asserts request line

° t2: Slave asserts ack, indicating ready to transmit data

° t3: Master releases req, data received

° t4: Slave releases ack

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The I/O Bus Problem

I/O BUS

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PCI: Peripheral Component Interconnect

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PCI Read/Write Transactions

° All signals sampled on rising edge

° Centralized Parallel Arbitration

° All transfers are (unlimited) bursts

° Address phase starts by asserting FRAME#

° Next cycle “initiator” asserts cmd and address

° Data transfers happen on when• IRDY# asserted by master when ready to transfer data

• TRDY# asserted by target when ready to transfer data

• transfer when both asserted on rising edge

° FRAME# deasserted when master intends to complete only one more data transfer

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PCI Read Transaction

– Turn-around cycle on any signal driven by more than one agent

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PCI Write Transaction

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PCI Optimizations

° Push bus efficiency toward 100% under common simple usage

• like RISC

° Bus Parking• retain bus grant for previous master until another makes request

• granted master can start next transfer without arbitration

° Arbitrary Burst length• intiator and target can exert flow control with xRDY

• target can disconnect request with STOP (abort or retry)

• master can disconnect by deasserting FRAME

• arbiter can disconnect by deasserting GNT

° Delayed (pended, split-phase) transactions• free the bus after request to slow device

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1993 Backplane/IO Bus Survey

Bus SBus TurboChannel MicroChannel PCI

Originator Sun DEC IBM Intel

Clock Rate (MHz) 16-25 12.5-25 async 33

Addressing Virtual Physical Physical Physical

Data Sizes (bits) 8,16,32 8,16,24,32 8,16,24,32,648,16,24,32,64

Master Multi Single Multi Multi

Arbitration Central Central Central Central

32 bit read (MB/s) 33 25 20 33

Peak (MB/s) 89 84 75 111 (222)

Max Power (W) 16 26 13 25

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SCSI: Small Computer System Interface

° Asynchronous Bus

° Distributed Arbitration by Self-selection

° Data transfers happen on when:• C/D is deasserted by initiator

• I/O determines transfer direction between initiator & target

• REQ is asserted by target to request transfer cycle

• ACK is asserted by initiator when it has completed a transfer

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SCSI Signals Description

Signal Description

BSY indicates that the bus is being used

SEL used by an initiator to select a target, or by a target to reselect an initiator.

C/D indicates control or data information is on the data bus

I/0 control the direction of data movement on the data bus

MSG driven by a target during the Message phase

REQ driven by a target to request a REQ/ACK handshake

ACK driven by an initiator to acknowledge a REQ/ACK

ATN driven by an initiator to indicate the attention condition (indicator has a message for the target).

RST hard reset condition

DB • 8 data-bit signals, plus a parity-bit signal that form a Data Bus

• DB(7) is the most significant bit and has the highest prioty

• Bit number, significance, and priority decrease downward

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SCSI Arbitration

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SCSI Read/Write Transactions

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SCSI Roadmap

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SCSI Bus Characteristics

Type Bus Width

(bits)Bus Speed(MB's/sec)

Max.Devices

Bus Length (Meters)

SCSI-1 8 5 8 6

Fast SCSI 8 10 8 3

Ultra SCSI 8 20 8 1.5

Ultra2 SCSI LVD 8 40 8 12

Fast Wide SCSI 16 20 16 3

Ultra Wide SCSI 16 40 16 1.5

Ultra2 Wide SCSI 16 80 16 12

Ultra3 SCSI 16 160 16 12

Ultra320 SCSI 16 320 16 12

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Summary of Bus Options

°Option High performance Low cost

°Bus width Separate address Multiplex address& data lines & data lines

°Data width Wider is faster Narrower is cheaper (e.g., 32 bits) (e.g., 8 bits)

°Transfer size Multiple words has Single-word transferless bus overhead is simpler

°Bus masters Multiple Single master(requires arbitration) (no arbitration)

°Clocking Synchronous Asynchronous

°Protocol pipelined Serial