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IKI10230Pengantar Organisasi Komputer

Bab 12: Memori

Sumber:1. Paul Carter, PC Assembly Language2. Hamacher. Computer Organization, ed-53. Materi kuliah CS61C/2000 & CS152/1997, UCB

19 Mei 2004

L. Yohanes Stefanus (yohanes@cs.ui.ac.id)Bobby Nazief (nazief@cs.ui.ac.id)

bahan kuliah: http://www.cs.ui.ac.id/kuliah/POK/

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Memori: Tempat Penyimpanan Data

Processor (active)

Computer

Control(“brain”)

Datapath(“brawn”)

Devices

Input

Output

Keyboard, Mouse

Display, Printer

Disk (permanentstorages)

Memory(passive)

(where programs, data live whenrunning)

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Connection: Memory - Processor

MAR

MDR

Processor Memory

Panjang word= n bits

Sampai 2k addressablelocations

k-bit address bus

n-bit data bus

Control lines,R/W, MFC, etc.

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Organisasi Internal Memori

° Bentuk array: terdiri dari sel memori • Sel berisi 1 bit informasi• Baris dari sel membentuk untaian satu word• Contoh: 128 x 8 memori

- memori mengandung 128 word- setiap word terdiri dari 8 bit data- Kapasitas memori: 128 x 8 = 1024 bit

• Address Decoder digunakan untuk memilih baris word mana yang akan diakses

- alamat merupakan indeks dari baris pada array tersebut

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Organisasi Memori: 1-level-decode SRAM (128 x 8)

Addressdecoder

Addressdecoder

A0

A1

A6

sense/writeamps

sense/writeamps

b7’b7

d7

sense/writeamps

sense/writeamps

b1’b1

d1

sense/writeamps

sense/writeamps

b0’b0

d0Input/output lines

W0

W1

W127

memorycells

R/W’

Word 8 bit data

128 words

CS

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Static RAM (SRAM)

° SRAM dapat menyimpan “state” (isi RAM) selama terdapat “tegangan” power supply

° Sangat cepat, 10 nano-detik

° Densitas (bits per chip) rendah memerlukan 6 transistor per-sel mahal

° Pilihan teknologi untuk memori yang sangat cepat dengan kapasitas kecil cache

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Review: Static RAM Cell6-Transistor SRAM Cell

b’ b

word(row select)

° Write:1. Drive bit lines sesuai dengan bit (mis. b = 1, b’ = 0)2. Select row store nilai b dan b’ menjadi state latch

° Read:1. Precharge (set) bit lines high2. Select row3. Sense amp mendeteksi bit lines mana yang low state bit

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0 1

T T

Latch menyimpan state 1 bitTransistor T bertindak sebagai switchContoh: state 1

Latch dapat berubah dengan:- put bit value pada b dan b’ - word line pull high (select)

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Dynamic RAM (DRAM)

° Slower than SRAM • access time ~60 ns (paling cepat: 35 ns)

° Nonpersistant • every row must be accessed every ~1 ms

(refreshed)

° Densitas tinggi: 1 transistor/bit • Lebih murah dari SRAM • ~$1/MByte [2002]

° Fragile• electrical noise, light, radiation

° Pilihan teknologi memori untuk kapasitas besar dan “low cost” main memory

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Review: 1-Transistor Memory Cell (DRAM)

° Write:• 1. Drive bit line• 2. Select row (T sebagai switch)

° Read:• 1. Select row• 2. Sense Amp (terhubung dengan bit line): sense & drives

sesuai dengan value (threshold)• 3. Write: restore the value (high or low)

° Refresh• Just do a dummy read to every cell.

row select

bit

TC

Kapasitor menyimpan state 1 (charged) atau 0 (discharge)Perlu refresh!

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Classical DRAM Organization (square)

row

decoder

rowaddress

Column Selector & I/O Circuits Column

Address

data

RAM Cell Array

word (row) select

bit (data) lines

° Row and Column Address together:

• Select 1 bit a time

Each intersection representsa 1-T DRAM Cell

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DRAM-based Memory Systems

DRAM2^n x 1chip

DRAMController

address

Bus Drivers

n

n/2

(Row & ColumnAddresses)

w

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Operasi DRAM

° Row Address (~50ns)• Set Row address pada address lines & strobe

RAS• Seluruh row dibaca & disimpan di column

latches• Isi dari row memori cells akan di-refresh

° Column Address (~10ns)• Set Column address pada address lines &

strobe CAS• Access selected bit

- READ: transfer from selected column latch to Dout

- WRITE: Set selected column latch to Din

° Rewrite/Refreshed (~30ns)• Write back entire row

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DRAM: Kinerja

° Timing• Access time = 60ns < cycle time = 90ns• Need to rewrite row• Model asinkron: operasi memori dilakukan oleh

controller circuit delayprosesor menunggu sampai cycle time selesai lalu melakukan request lagi.

° Must Refresh Periodically• Perform complete memory cycle for each row• Approx. every 1ms• Handled in background by memory controller

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Perkembangan Teknologi Memori DRAM

° Teknologi memori: segi kecepatan akses berkembang sangat lambat

• Gap yang semakin membesar dengan kecepatan prosesor (cycle sangat kecil => 1 nsec, akses memori orde puluhan nsec).

° Perkembangan teknologi DRAM• Basis tetap sama: 1-transistor memori cell

(menggunakan kapasitor)• Inovasi dilakukan dari cara melakukan akses

- memotong waktu akses (mis. CAS tidak diperlukan)

- burst mode: sekaligus mengambil data sebanyak mungkin (seluruh word)

- perlu tambahan rangkaian: register, latch dll

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Enhanced Performance DRAMs

° Conventional Access• Row + Col• RAS CAS RAS CAS ...

° Page Mode• Row + Series of columns• RAS CAS CAS CAS ...• Gives successive bits

° Video RAM• Shift out entire row sequentially• At video rate

Rowaddress

latch

Rowaddress

latch

Columnaddress

latch

Columnaddress

latch

Row decoder

Row decoder 256x256

cell array

256x256cell array

sense/writeamps

sense/writeamps

columndecoder& latch

columndecoder& latch

A15-A8/A7-A0

\8

\8

R/W’

CAS

RAS

row

col

Entire row buffered here

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Fast Page Mode Operation

° Fast Page Mode (FPM) DRAM• N x M “SRAM” to save a row

° After a row is read into the register

• Only CAS is needed to access other M-bit blocks on that row

• RAS’ remains asserted while CAS’ is toggled

° EDO DRAM• More modern FPM DRAM

A Row Address

CAS’

RAS’

Col Address Col Address

1st M-bit Access

N r

ows

N cols

DRAM

ColumnAddress

M-bit OutputM bits

N x M “SRAM”

RowAddress

Col Address Col Address

2nd M-bit 3rd M-bit 4th M-bit

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SDRAM & DDR SDRAM° SDRAM: Synchronous DRAM

• Address & Data are buffered in registers• Burst Mode:

- Read/Write of different data lengths CAS signals are provided internally

• Standards: PC100, PC133

° DDR SDRAM: Double-Data-Rate SDRAM• Data is transferred on both edges of the clock• Cell array is organized in 2 banks

allows interleaving of word’s access• Standards: PC2100, PC2300

° RDRAM: Rambus DRAM• High transfer rate using differential signaling• Data is transferred on both edges of the clock• Memory cells are organized in multiple banks• Standards: proprietary owned by Rambus Inc.

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Read-Only Memory° ROM – Read Only Memory

• ROMs are RAMs with data built-in when the chip is created. Usually stores BIOS info. Older uses included storage of bootstrap info

• Write once, by manufacturer° PROM – Programmable ROM

• A ROM which can be programmed• Write once, by user

° EPROM – Erasable PROM• A PROM which can be programmed, erased by exposure to UV

radiation° EEPROM – Electrically, Erasable PROM

• A PROM programmed & erased electrically° Flash

• ~EEPROM• Write in blocks• Low power consumption battery driven• Implementation:

- Flash Cards- Flash Drives:

– Better than disk (no movable parts faster response)

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MEMORY HIERARCHY

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Memory Hierarchy (1/4)

° Prosesor• menjalankan program• sangat cepat waktu eksekusi dalam orde

nanoseconds sampai dengan picoseconds• perlu mengakses kode dan data program!

Dimana program berada?

° Disk• HUGE capacity (virtually limitless)• VERY slow: runs on order of milliseconds

° So how do we account for this gap?

Menggunakan teknologi hierarki memori!

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Memory Hierarchy (2/4)

° Memory (DRAM)• Kapasitas jauh lebih besar dari registers, lebih kecil

dari disk (tetap terbatas)• Access time ~50-100 nano-detik, jauh lebih cepat

dari disk (mili-detik)• Mengandung subset data pada disk (basically

portions of programs that are currently being run)

° Fakta: memori dengan kapasitas besar (murah!) lambat, sedangkan memori dengan kapasitas kecil (mahal) cepat.

° Solusi: menyediakan (ilusi) kapasitas besar dan akses cepat!

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Memory Hierarchy (3/4)

Processor

Size of memory at each level

Increasing Distance

from Proc.,Decreasing

cost / MB

Level 1

Level 2

Level n

Level 3

. . .

Higher

Lower

Levels in memory

hierarchy

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Memory Hierarchy (4/4)

° Pada tingkat yang lebih dekat dengan Prosesor, mempunyai karakteristik:

• Lebih kecil,• Lebih cepat,• Menyimpan subset dari data (mis. menyimpan

data yang sering digunakan),• Efisien dalam pemilihan mana data yang akan

disimpan, karena tempat terbatas

° Tingkat paling rendah (biasanya disk) menyimpan seluruh data

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Memory Hierarchy Analogy: Library (1/2)

° You’re writing a term paper (Processor) at a table in Doe

° Doe Library is equivalent to disk• essentially limitless capacity• very slow to retrieve a book

° Table is memory• smaller capacity: means you must return book when

table fills up• easier and faster to find a book there once you’ve

already retrieved it

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Memory Hierarchy Analogy: Library (2/2)

° Open books on table are cache• smaller capacity: can have very few open books

fit on table; again, when table fills up, you must close a book

• much, much faster to retrieve data

° Illusion created: whole library open on the tabletop

• Keep as many recently used books open on table as possible since likely to use again

• Also keep as many books on table as possible, since faster than going to library

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Why hierarchy works° The Principle of Locality:

• Program access a relatively small portion of the address space at any instant of time.

Address Space0 2^n - 1

Probabilityof reference

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Memory Hierarchy: How Does it Work?° Temporal Locality (Locality in Time):

Keep most recently accessed data items closer to the processor

° Spatial Locality (Locality in Space): Move blocks consists of contiguous words

to the upper levels

Lower LevelMemoryUpper Level

MemoryTo Processor

From ProcessorBlk X

Blk Y

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Memory Structure in Modern Computer System

° By taking advantage of the principle of locality:• Present the user with as much memory as is available in the

cheapest technology.• Provide access at the speed offered by the fastest

technology.

Control

Datapath

SecondaryStorage(Disk)

Processor

Registers

MainMemory(DRAM)

SecondLevelCache

(SRAM)

On

-Ch

ipC

ache

1s 10,000,000s (10s ms)

Speed (ns): 10s 100s

100sGs

Size (bytes):Ks Ms

TertiaryStorage(Tape)

10,000,000,000s (10s sec)

Ts

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How is the hierarchy managed?

° Registers ↔ Memory• by compiler (programmer?)

° Cache ↔ Memory• by the hardware

° Memory ↔ Disks• by the hardware and operating system (virtual

memory)• by the programmer (files)