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Interface Circuits

An I/ O inter f ace consists of the cir cuitr y r equir ed to connect an I/ O device

to a computer bus. On one side of the inter f ace, we have bus signals. On the

other side, we have a data path with its associated contr ols to tr ansf er data

between the inter f ace and the I/ O device – port. We have two ty pes : Ser ial

port and Par alle

l por t.

A par allel port tr ansf er s data in the form of a number of bits (8 or 16)

simultaneously to or from the device. A ser ial port tr ansmits and r eceives data

one bit at a time. Communication with the bus is the same for both f or mats.

The conver sion from the par allel to the ser ial f or mat, and vice versa, takes

place inside the inter f ace cir cuit. In par allel port, the connection between the

device and the computer uses a multi ple- pin connector and a ca ble with as

many wir es. This arrangement is suita ble for devices that are physically close to

the computer. In ser ial port, it is much more convenient and cost-eff ective

where longer ca bles ar e needed.

Ty pically, the f unctions of an I/ O inter f ace ar e:

Pr ovides a storage buffer for at least one word of data

Contains status f lags that can be accessed by the processor to

deter mine whether the buffer is full or empty

Contains addr ess-decoding cir cuitr y to deter mine when it is being

addr essed by the pr ocessor

Generates the a ppr o pr iate timing signals r equir ed by the bus contr ol

scheme

Performs any format conver sion that may be necessary to tr ansf er data

between the bus and the I/ O device, such as par allel-ser ial conver sion in

the case of a ser ial por t

Parallel Port The hardware components needed for connecting a keyboard to a

processor . Consider the circuit of in put inter f ace which encompasses (as shownin below f igur e): Status f lag/SI N, R / ~W, Master -r eady, Addr ess decoder.

The hardware components needed for connecting a pr inter to a processor

ar e : the circuit of output inter f ace, and Slave-r eady, R / ~W, Master -r eady,

Addr ess decoder, Handshake contr ol.

The in put and output inter f aces can be combined into a single inter f ace.

The gener al purpose par allel inter f ace circuit that can be conf igur ed in a var iety of

ways. For incr eased f lexi bility, the circuit makes it possi ble for some lines to

serve as in puts and some lines to serve as outputs, under program contr ol.

Serial Port A ser ial inter f ace circuit involve chip and r egister select, Status and

contr ol, Output shif t r egister , DATAOUT, DATAI N, Input shif t r egister and Ser ial

in put/ out put.

Standard I/ O interf aces

Consider a computer system using diff er ent inter f ace standards. Let us

look in to Processor bus and Per i pher al Component Interconnect (PCI) bus.




These two buses are inter connected by a circuit called br idge. It is a br idge

between processor bus and PCI bus. The three major standard I/ O inter f aces

discussed here ar e : PCI (Per i pher al Component Inter connect), SCSI (Small

Computer System Inter f ace), USB (Univer sal Ser ial Bus), PCI (Per i pher al

Component Inter connect).

The to pics d

iscussed under PCI are: Data Tr ansf er , Use of a PCI bus in a

computer system, A read o per ation on the PCI bus, Device conf igur ation and

Other electr ical char acter istics.

Host, main memory and PCI br idge are connected to disk , pr inter and

Ethernet inter f ace through PCI bus. At any given time, one device is the bus

master. It has the r ight to initiate data tr ansf er s by issuing read and wr ite

commands. A master is called an initiator in PCI ter minology. This is either

processor or DMA contr oller . The addressed device that responds to read and

wr ite commands is called a target. A complete tr ansf er o per ation on the bus,

involving an address and a burst of data, is called a tr ansaction. Device

conf igur ation is also discussed.

SCSI Bus It is a standard bus def ined by the Amer ican National Standards Institute

(A NSI). A contr oller connected to a SCSI bus is an initiator or a target. The

processor sends a command to the SCSI contr oller , which causes the

following sequence of events to take place:

The SCSI contr oller contends for contr ol of the bus (initiator ).

When the initiator wins the ar bitr ation process, it selects the target

contr oller and hands over contr ol of the bus to it.

The target starts an output o per ation. The initiator sends a command

s pecif ying the r equir ed read oper ation.

The target sends a message to the initiator indicating that it will

tempor ar ily suspends the connection between them. Then it r eleases the

bus.

The target contr oller sends a command to the disk dr ive to move the

r ead head to the f ir st sector involved in the requested read o per ation.

The target tr ansf er s the contents of the data buffer to the initiator and

then suspends the connection again.

The target contr oller sends a command to the disk dr ive to perform

another seek oper ation.

As the initiator contr oller r eceives the data, it stores them into the main

memory using the DMA a ppr oach.

The SCSI contr oller sends an interru pt to the processor to inf or m it that

the requested o per ation has been completed.

The bus signals, ar bitr ation, selection, inf or mation tr ansf er and r eselection are

the to pics discussed in addition to the a bove.




Universal Serial Bus (USB)

The USB has been designed to meet sever al key objectives such as :

Pr ovide a simple, low-cost and easy to use inter connection system that

overcomes the difficulties due to the limited number of I/ O ports

availa ble on a computer

Accommodate a wide range of data tr ansf er char acter istics for I/ O devices, including tele phone and Internet connections

Enhance user convenience through a “ plug-and- play” mode of o per ation

Port Limitation

Here to add new ports, a user must open the computer box to gain access

to the internal ex pansion bus and install a new inter f ace card. The user may also

need to know how to conf igur e the device and the sof twar e. And also it is to

make it possi ble to add many devices to a computer system at any time,

without o pening the computer box.

Device Characteristics

The k inds of devices that may be connected to a computer cover a wide

r ange of f unctionality - speed, volume and timing constr aints. A var iety of

simple devices attached to a computer generate data in diff er ent

asynchronous mode. A signal must be sampled quickly enough to track its

highest-f r equency components.

Plug-and-play

Whenever a device is intr oduced, do not turn the computer off / r estar t

to connect/ disconnect a device. The system should detect the existence of

this new device automatically, identif y the a ppr opr iate device-dr iver softwareand any other facilities needed to ser vice that device, and esta blish the

a ppr opr iate addresses and logical connections to ena ble them to

communicate.

USB architecture

To accommodate a lar ge number of devices that can be added or removed

at any time, the USB has the tree structure. Each node has a device called a

hub. Root hu b, f unctions, s plit bus o per ations – high speed (HS) and Full/ Low

speed (F/ LS).

5114100067 dzaky zakiyal fawwaz rangkuman bab7

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