pci target ip - 京微雅格€¦ · req_n o 1 request pci bus. active low. only present when...

PCI Target IP

Design Guide

02/2014

Capital Microelectronics, Inc.

China

Design Guide of PCI Target IP

http://www.capital-micro.com 2

Contents

Contents ..................................................................................................................................................2

1 Introduction ......................................................................................................................................3

2 PCI Target IP Overview .......................................................................................................................4

2.1 Pin Description ..................................................................................................................................... 4

2.2 PCI Target IP Diagram ........................................................................................................................... 7

2.2.1 Target Control ...................................................................................................................................... 8

2.2.2 Configuration Registers ........................................................................................................................ 8

2.2.3 PCI Slave IP Parameter ....................................................................................................................... 12

2.3 PCI Transaction ................................................................................................................................... 13

2.3.1 Configuration Write/Read .................................................................................................................. 13

2.3.2 Bar0 single Write/Read ...................................................................................................................... 15

2.3.3 Bar1-Bar5 single Write/Read ............................................................................................................. 17

2.3.4 Interrupt............................................................................................................................................. 19

2.3.5 Abort and Retry ................................................................................................................................. 19

2.4 IO Standard Definition ........................................................................................................................ 21

3 PCI Target IP Generation .................................................................................................................. 22

3.1 PCI Target IP Generation ..................................................................................................................... 22

3.2 Resource Usage and Performance Analysis ........................................................................................ 24

4 Generate File Directory Structure ..................................................................................................... 25

Revision History ..................................................................................................................................... 27



1 Introduction

This document mainly describes an example design of the PCI Target IP. This PCI Target IP provides a PCI

(peripheral component interconnect) interface, with which FFGA can communicate with PCI host. The PCI

Target IP supports the following features:

Fully compliant with PCI v2.2 specification

Implements the PCI Target function

32bit data and address bus

33 MHz or 66MHz speed options

Up to 6 target channels

Support up to 32 interrupt requests

Single cycle support for read and write cycles

Parity generation for all read cycles

Note: Burst mode will be supported in PCI Target IP v2.

Device family support:

CME-M5, CME-M7



2 PCI Target IP Overview

2.1 Pin Description

Table 2-1 PCI Target IP Interface

Name Type Size Description

PCI interface

ad I/O 32 The multiplexed PCI address/data bus

cbe_n I 4 The multiplexed PCI command/byte enables

par I/O 1 The even parity bit. The PCI target drives this

signal during read cycles. The PCI initiator

drives this signal during the address phase of

all transactions and the data phase during

writes.

frame_n I 1 The PCI initiator drives this signal low at the

beginning of a cycle and high at the clock edge

before the last data phase on a burst

operation.

irdy_n I 1 The PCI initiator drives the signal low prior to

the positive edge of a clock when it can

complete a data phase.

trdy_n I/O 1 The PCI target drives this signal low prior to

the positive edge if a clock when it can

complete a data phase.

peer_n I/O 1 Peer IO indicates that a parity error was

detected during the target write transfer or

initiator read transfer.

seer_n I/O 1 Indicates that a parity error was detected

during an address cycle, except during special

cycles.

devsel_n I/O 1 The PCI target drives DEVSEL low to indicate

the address of the current transaction is in the

address space of one of the base address

registers.

req_n O 1 Request PCI Bus. Active low. Only present

when Master interface is implemented.

gnt_n I 1 PCI Bus Granted. Active low. Only present

when Master interface is implemented.

stop_n O 1 PCI stop signal output. Active low.

m66_en O 1 When high, PCI bus clock is running at 66MHz.

Idsel I 1 The PCI initiator will drive the IDSEL signal high



at the input of the PCI target that should

complete the current configuration cycle on

the PCI bus

lock_n I 1 PCI bus lock signal

clk I 1 The clock input to all PCI devices on the PCI

bus including PCI targets, PCI initiators and PCI

arbiters.

rst_n I 1 The active low reset for all PCI devices on the

PCI bus.

int_a_n O 1 The interrupt signal passed through the PCI

target from the back end device.

Local Interface

BAR0

bar0_wr O 4 Bar0 write enable, "1" available:

bar0_wr[3:0] : 0001 write 7:0 bit

0010 write 15:8 bit

0100 write 23:16 bit

1000 write 31:24 bit

bar0_rd O 4 Bar0 read enable, "1" available:

bar0_rd[3:0] : 0001 read 7:0 bit

0010 read 15:8 bit

0100 read 23:16 bit

1000 read 31:24 bit

bar0_datai I 32 Bar0 data input

bar0_datao O 32 Bar0 data output

bar0_addr O 32 Bar0 address output

BAR1






bar1_cbe O 4 Bar1 byte enable

bar1_cbe: 1110: 7:0 bit available

1101: 15:8 bit available



BAR2









Bar2_cbe: 1110: 7:0 bit available




BAR3











BAR4











BAR5











Local Control signal

force_retry I 1 When asserted, forces the core to respond to

all PCI transactions in its address ranges with a

retry. This may be useful if the backend

circuitry performs some initialization routine at



startup.

force_abort I 1 When asserted, forces the core to respond to

all PCI transactions in its address ranges with a

target abort. This may be useful if the backend

circuitry detects a fatal error and determines

that it can nolonger function, and in allowing a

target abort when certain addresses are

accessed.

Int_req I 32 Local interrupt request, "1" available

2.2 PCI Target IP Diagram

PCI Bus

PCI Interface

Configuration Register

Local Interface

bar0 bar1 bar2 bar3 bar4 bar5

PCI Slave IP

PCI Target Bus

Local Bus:1. Data bus barN_wr, barN_rd, barN_datai, barN_datao, barN_cbe, barN_addr

Notes: the ‘N’is the number of Bar.2. System singleInterrupt,retry,abort

Figure 2-1 PCI Slave IP block diagram



PCI Bus

PCI Interface

CMDDecoder

TargetState

Machine

Config RegisterBlock

OutputData MUX

Bar0-Bar5

Local Logic

Target Control

PCI Target Bus

Local Bus

Figure 2-2 PCI Slave IP dataflow diagram

Figure 2-1 illustrates the overall architecture of the PCI slave IP and Figure 2-2 illustrates the PCI Slave IP

dataflow diagram.

2.2.1 Target Control

The Target Control logic consists of a CMD Decoder and a Target State Machine.

2.2.1.1 CMD Decoder

The CMD Decoder decodes the command from PCI bus signal C/BE#[3:0]. The commands listed below are

decoded; other commands are ignored:

Memory Read/Write

Memory read multiple/memory read line (aliased to memory read)

Memory write and invalidate (aliased to memory write)

I/O read/write

Configuration read/write

The CMD Decoder also includes an Address latch.

2.2.1.2 Target State Machine

The Target State Machine generates control cycles for the MPCI32 core in response to PCI bus requests, based

on the information from the CMD Decoder.

If the address is not appropriate, or if the backend is busy fetching or storing data, a Target abort or Target

retry cycle will be generated by the state machine.

2.2.2 Configuration Registers

The Configuration registers are contained completely within the MPCI32 core.



Address Offset Register Name Wizard Manager

Setting

Description

01h-00h Vendor_ID Y Unique Manufacturer ID – Reset value

factory-configured

03h-02h Device_ID Y Unique Device ID – Identifies the device as per

vendor ID.

05h-04h Command N Bit0 – I/O Space Enable

Bit1 – Memory Space Enable

Bit2 – Bus Master Enable

Bit3 – Not implemented. Always reads zero

Bit4 – Memory Write +Invalidate Enable.

Bit5 – Not implemented. Always reads zero

Bit 6 – Parity Error Response

Bit 7 – Not implemented. Always reads zero

Bit 8 – SERR# Enable

Bit 9 – Fast Back to Back Enable

Bits 15:10 – Reserved. Always read zero

07h-06h Status N Bits 3:0 – Reserved. Always read zero

Bit 4 – Capabilities list present . Set to ‘1’ if

power management interface present.

Bit 5 – 66MHz capable . Factory-configured. Set

to ‘1’ if core can run at 66MHz.

Bit 6 – Reserved. Always reads zero

Bit 7 – Fast back-to-back capable . Always read as

‘1’ because target is capable of accepting fast

back-to-back transfers.

Bit 8 – Master data parity detected. Latched

status bit: write ‘1’ to reset it.

Bits 10:9 – DEVSEL timing. Always reads ‘01’ =

medium.

Bit 11 – Signaled target abort . Latched status bit:

write ‘1’ to reset it.

Bit 12 – Received target abort. Latched status bit:

write ‘1’ to reset it.

Bit 13 – Received master abort. Latched status

bit: write ‘1’ to reset it.

Bit 14 – Signaled system error . Latched status

bit: write ‘1’ to reset it.

Bit 15 – Detected parity error . Latched status bit:

write ‘1’ to reset it

08h Revision ID Y Revision identifier of device.

0Bh-09h Class Code N Class Code

0Ch Cache Line Size N Cache Line Size. All cache line sizes that are

powers of two are supported.



Only presented when master is implemented

0Dh Latency Timer N Bus Latency Timer. Bits [2:0] hardwired to zero to

give granularity of 8 clocks. Only presented when

master is implemented

0Eh Header Type N Defines Type 0 configuration header layout as

per PCI spec.

0Fh BIST N Not implemented. Always reads zero

13h-10h Base Address

Register 0

Y Bit 0 – Memory / I/O space indicator. Factory

configured.

When Bit 0 = 0 (Target mapped to Memory

space)

Bit 1 – From PCI side of

core :Factory-configured and Read-only. Set

to ‘1’ if located below 1MB address

boundary .From backend interface : When

written with ‘1’, BAR ‘disappears’ (read back

as zero or unimplemented) and target

ignores all access to its

address range. Target and BAR return to

normal operation when bit written with ‘0’.

Bit 2 – always reads 0

Bit 3 (read only) – Set to ‘1’ if memory region

to which target is mapped is prefetchable.

Note: If target is register type, this bit will

always return zero.

Bits 31-4 – MSBs written by the system

startup software with the base address of

target address range. Number of active bits

factory-configured in line with amount of PCI

Address Space allocated to target. Remaining

bits hardwired to zero.

When Bit 0 = 1 (Target mapped to I/O space)

Bit 1 – From PCI side of core: Reserved,

always reads zero.

From backend interface : As for

‘Memory space’ option above.

Bits 31-2 – MSBs written by the system

startup software with the base

address of target address range.

Number of active bits

factory-configured in line with amount

of PCI Address Space allocated to

target. Remaining bits hardwired to

zero.




Register 1

Y As Base Address Register 0. If target channel not

implemented, always reads zero.

1Bh-18h Base Address

Register 2



1Fh-1Ch Base Address

Register 3




Register 4




Register 5



2Bh-28h Cardbus CIS

Pointer

N Pointer to Cardbus data structure

2Dh-2Ch Subsystem

Vendor ID

Y 2byte Subsystem Vendor ID.

2Fh-2Eh Subsystem ID Y 2byte Subsystem ID.

33h-30h BIOS ROM Base

Address Register

N Bit 1 – ROM Address decoder enable. The BIOS

ROM address space is

read only and the target will only respond when

this bit is set to ‘1’.

Bits 10:1 – Reserved. Always read zero

Bits 31:11 – MSBs written by the system startup

software with the base

address of BIOS ROM address range. Number of

active bits factory-configured in line with amount

of PCI Address Space allocated to BIOS

ROM. Remaining bits hardwired to zero

34h Capabilities

Pointer

N Points to the first capabilities structure which will

either be the power

management registers at 40h or the vital product

data at 4Ch, or nothing

(00h)

3Bh-35h Reserved N Always reads zero.

3Ch Interrupt Line N Programmable in a PC environment to a number

between 0 and 15 corresponding to the interrupt

channel assigned to this device. For information

only

3Dh Interrupt Pin N Indicates device uses INTA#

3Eh Min_Gnt Y Minimum requested bus grant duration. Reads

zero if the Master interface is not

implemented

3Fh Max_lat Y Maximum requested bus grant latency. Reads

zero if the Master interface is not

implemented



2.2.3 PCI Slave IP Parameter

When use the PCI Slave IP, there are some parameter need to be set.

BAR0_EXSIT:

PCI Bar0 exists.

BAR1_EXSIT:

PCI Bar1 exists.

BAR2_EXSIT:

PCI Bar2 exists.

BAR3_EXSIT:

PCI Bar3 exists.

BAR4_EXSIT:

PCI Bar4 exists.

BAR5_EXSIT:

PCI Bar5 exists.

BAR0_TYPE:

0: IO; 1: Memory

BAR1_TYPE:

0: IO; 1:Memory

BAR2_TYPE:

0:IO; 1:Memory

BAR3_TYPE:

0:IO;1:Memory

BAR4_TYPE:

0:IO;1:Memory

BAR5_TYPE

0:IO;1:Memory

BAR0_SIZE:

Size of BAR0, the value is the power of 2.

BAR1_SIZE:


BAR2_SIZE;


BAR3_SIZE;


BAR4_SIZE;


BAR5_SIZE


VENDOR_ID

Manufacturer identifier of the device.

DEVICE_ID

Identifier of device.

REVISION_ID



Revision identifier of device.

SUB_VENDOR_ID

Sub Manufacturer identifier of the device.

SUB_DEVICE_ID

Sub Identifier of device.

BASE_CLASS

Function type of device.

SUB_CLASS

Function type of device.

INTERFACE

Register-Level programming interface.

MAX_LATENCY

The value of Max latency.

MIN_GRANT

The time of burst transfer.

PCI_33M

PCI Clock 33M or 66M

2.3 PCI Transaction

2.3.1 Configuration Write/Read

The PCI target only responds to certain types of configuration transactions. The HDL is coded so the target

only responds to type 00 transactions (PCI_AD[1:0] == 00b) directed at function 0 (PCI_AD[10:8] == 000b).

During con-figuration cycles, the address bits PCI_AD[7:2] determine which configuration double word is

being accessed, while the PCI_CBE_L[3:0] bits determine if the cycle is a configuration read or configuration

write.

The target will respond to configuration reads to unimplemented registers, and return a value of 0000_0000h.

The target will respond to writes to a configuration register that is not implemented, although the data will

never be writ-ten.

Burst addressing of the configuration registers is uncommon and is not supported.



Figure 2-3 Configuration Read

Figure 2-4 Configuration Write



2.3.2 Bar0 single Write/Read

Figure 2-5 Bar0 single Read

Figure 2-6 Bar0 single Write



Figure 2-7 Bar0 Burst Write

Figure 2-8 Bar0 Burst Read



2.3.3 Bar1-Bar5 single Write/Read

Figure 2-9 Bar1-5 single Read

Figure 2-10 Bar1-5 single Write



Figure 2-11 Bar1-5 Burst Write

Figure 2-12 Bar1-5 Burst Read



2.3.4 Interrupt

Figure 2-13 PCI Interrupt

2.3.5 Abort and Retry

force_retry: When asserted, forces the core to respond to all PCI transactions in its address ranges with a retry.

This may be useful if the backend circuitry performs some initialization routine at startup.

force_abort: When asserted, forces the core to respond to all PCI transactions in its address ranges with a

target abort. This may be useful if the backend circuitry detects a fatal error and determines that it can no

longer function, and in allowing a target abort when certain addresses are accessed.



Figure 2-14 PCI Retry

Figure 2-15 PCI Abort



2.4 IO Standard Definition

In accordance with PCI specification, those pins connected to PCI bus should comply with PCI logic level. For

CME M7, every IO pin supports the logic level. It is configured via IO editor, as the following figure 2-16.

Figure 2-16 PCI Logic Level Configuration in IO Editor

For CME M5, uses can insert a resistor(33 ohms recommended) between M5 chip and PCI bus slot of the

motherboard to keep from the damage of high-voltage.



3 PCI Target IP Generation

3.1 PCI Target IP Generation

Step1: Open the Wizard Manager and choose the PCI.

Figure 3-1 PCI Target IP Generate Step1

Step2: Define the name of PCI Target IP.




Step3: Configuration Information Setting


Step4: Address and Type setting.




Step5: Clock select


3.2 Resource Usage and Performance Analysis

Resource usage and performance of the PCI Target IP are listed in table 3-1.

Table 3-1 PCI Target IP resource usage and performance

Chip Type LUTs Regs Performance

M5 780 510 110M

M7 800 510 110M



4 Generate File Directory Structure

The PCI Target IP wizard generated file includes: source files (src), simulation files(sim) and example design

files. The detailed design directory structure is as below.

Project

src outputs ip_core

pci_inst.v(define by user)

mpci_io.v

simsrc doc example

pci_tb.v CME_PCI_user_guide_EN01.pdf

example_M5example_M7

CME_PCI_example_user_guide_EN01.pdf

= directory

= source RTL code

= simulation related files

= documentation

mpci_io

pci_sim.do

src_vp

*.vp(Protected RTL)

pci_demo.v

pci_tb_modelsim.f

Figure 4-1 PCI Target IP wizard generated file directory structure

Table 4-1 Generated File Directory structure

Directory Description

src\ Directory for project source code, including IP

wizard generate code, for example: mpci_io.v,

which instantiate the PCI target IP and define

related parameters

ip_core\ The directory specially for all IPs

\mpci_io Directory for PCI IP

\doc\CME_PCI_user_guide_EN01.doc User guide for PCI IP

\src IP Design RTL

\src\mpci_io.v PCI Target core (Encrypted)

\sim Design Simulation Directory

\sim\pci_tb.v Test bench

\sim\pci_tb_modelsim.f File list of simulation related file

\sim\pci_sim.do Do file for ModelSim simulation

\sim\pci_demo.v A wrapper file



\src_vp Directory for protected design RTL for ModelSim

simulation

\*.vp Protected PCI Target IP design RTL

\example

example_M5.zip Example design for M5

example_M7.zip Example design for M7

CME_PCI_example_user_guide.pdf User guide of example design



Revision History

Revision Date Comments

1.0 2014-02-24 Initial release

pci target ip - 京微雅格€¦ · req_n o 1 request pci bus. active low. only present when...

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