Ejemplo:

1 library ieee;2 use ieee.std_logic_1164 .all;34 entity ejmss is5 port( w : in std_logic;6 clk, rstn : in std_logic;7 z : out std_logic);8 end ejmss;910 architecture behaviour of ejmss is11 type estado is (a,b,c);12 signal y: estado;13 begin14 process(clk,rstn)15 begin16 if rstn = '0' then y <= a;17 elsif (clk = '1' and clk'event) then18 case y is19 when a =>20 if w = '0' then y <= a;21 else y <= b; end if;22 when b =>23 if w = '0' then y <= a;24 else y <= c; end if;25 when c =>26 if w = '1' then y <= c;27 else y <= a; end if;28 end case;29 end if;30 end process;31 process(y,w)32 begin33 z <= '0';34 case y is35 when c => z <= '1';36 when others => z <= '0';37 end case;38 end process;39 end behaviour;