IEEE ELECTRON DEVICE LETTERS, VOL. 34, NO. 3, MARCH 2013 357

1.4-kV AlGaN/GaN HEMTs on aGaN-on-SOI Platform

Qimeng Jiang, Cheng Liu, Yunyou Lu, and Kevin J. Chen, Senior Member, IEEE

Abstract—We demonstrate high-voltage depletion-mode andenhancement-mode (E-mode) AlGaN/GaN high-electron-mobilitytransistors (HEMTs) on a GaN-on-silicon-on-insulator (SOI) plat-form. The GaN-on-SOI wafer features GaN epilayers grown bymetal–organic chemical vapor deposition on a p-type (111) SiSOI substrate with a p-type (100) Si handle wafer. Micro-Ra-man spectroscopy significantly reveals reduced stress in the GaNepilayers, which is a result expected from the compliant SOIsubstrate. E-mode HEMTs fabricated by fluorine plasma implan-tation technique deliver high ON/OFF current ratio (108−109),large breakdown voltage (1471 V with floating substrate), and lowON-resistance (3.92 mΩ · cm2).

Index Terms—AlGaN/GaN high-electron-mobility transistors(HEMTs), enhancement-mode (E-mode), fluorine plasma ion im-plantation, GaN-on-silicon-on-insulator (SOI), high voltage.

I. INTRODUCTION

A lGaN/GaN high-electron-mobility transistors (HEMTs)fabricated on a silicon substrate are promising candi-

dates for high-efficiency power switches and integrated powerconverters because of silicon wafers’ excellent scalability andfavorable device characteristics, including high breakdownvoltage, low ON-resistance, and high switching frequency [1],[2]. In order to achieve monolithic integration of GaN powerdevices and the gate drive circuits, a GaN smart power ICplatform has been demonstrated, delivering high-voltage com-ponents (transistors and rectifiers) and peripheral mixed-signalfunctional blocks on the same chip [3]. Another attractiveapproach is the heterogeneous integration of GaN HEMTand Si CMOS that could take advantage of the mature high-integration-density Si CMOS technology. The major challengefor such a heterogeneous integration is that GaN epigrowthprefers (111) Si, whereas the mainstream CMOS technologiesare developed on (100) Si substrates. Several heterogeneousintegration schemes have been reported, including wafer bond-ing [4], selective molecular beam epitaxy growth of GaN on(100) Si-SiO2-(111) Si silicon-on-insulator (SOI) wafers [5],and direct CMOS integration on (111) silicon substrate [6]. Itis noted, however, that high-voltage AlGaN/GaN HEMTs havenot been reported on these platforms.

Manuscript received November 28, 2012; revised December 18, 2012;accepted December 20, 2012. Date of publication January 14, 2013; date ofcurrent version February 20, 2013. This work was supported in part by theHong Kong Research Grant Council under Grant 611311 and Grant 611512.The review of this letter was arranged by Editor J. A. del Alamo.

The authors are with the Department of Electronic and Computer Engineer-ing, Hong Kong University of Science and Technology, Kowloon, Hong Kong(e-mail: qmjiang@ust.hk; eekjchen@ust.hk).

Color versions of one or more of the figures in this letter are available onlineat http://ieeexplore.ieee.org.

Digital Object Identifier 10.1109/LED.2012.2236637

Fig. 1. (a) Photograph of the 4-in GaN-on-SOI wafer. (b) SEM cross-sectionalview of the GaN-on-SOI wafer. (c) Schematic cross-sectional view of theD-mode and E-mode HEMT fabricated on the GaN-on-SOI platform.(d) Micro-Raman spectroscopy of the GaN-on-SOI and GaN-on-Si (bulk)wafers. (Inset) Mapping of the E2 peak on the GaN-on-SOI wafer.

In this letter, high-performance depletion-mode (D-mode)and enhancement-mode (E-mode) high-voltage AlGaN/GaNHEMTs with over 1400-V breakdown voltage were demon-strated on a GaN-on-SOI platform. The GaN-on-SOI waferfeatures GaN epilayer grown by metal–organic chemical vapordeposition (MOCVD) on a p-type (111) Si SOI substrate witha p-type (100) Si handle wafer. For future heterogeneous in-tegration with Si CMOS, the CMOS-compatible (100) siliconcould be selectively exposed by removing the materials on top,including GaN, (111) Si, and SiO2.

II. GaN-ON-SOI WAFER AND DEVICE FABRICATION

The photograph and the SEM cross-sectional view of the4-in AlGaN/GaN-on-SOI wafer used in this letter are shownin Fig. 1(a) and (b). A 4-μm-thick AlGaN/GaN epistructure(including 30-nm Al0.25Ga0.75N barrier, 1-μm unintentionallydoped GaN buffer, and 3-μm unintentionally doped transi-tion layer) was grown by MOCVD on a 4-in SOI wafer.The SOI wafer features a 5-μm (111) p-type Si layer, a0.2-μm SiO2 layer, and a 600-μm p-type (100) Si handle wafer,and it was fabricated by wafer bonding. For comparison, thesame AlGaN/GaN epistructure was also grown on a 4-in bulk(625-μm thick) p-type (111) Si wafer.

It has been proposed that the SOI wafer provides a compliantsubstrate that provides a good stress release to an epilayergrown on a substrate with large lattice-mismatch [7], [8]. The

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358 IEEE ELECTRON DEVICE LETTERS, VOL. 34, NO. 3, MARCH 2013

TABLE ICOMPARISON OF THE BASIC CHARACTERISTICS BETWEEN

THE SOI AND BULK SAMPLES

Fig. 2. DC characteristics of the D-mode and E-mode devices on the GaN-on-SOI wafer. (a) Source–drain I–V characteristics (unpassivated). (b) Transfercharacteristics in linear scale (unpassivated). The gate-to-drain distance of thesedevices is 10 μm.

micro-Raman spectroscopy was performed on our GaN-on-SOIwafer, and the results are shown in Fig. 1(d). The E2 peak wasfound to be 567.5 ± 0.2 cm−1, which is very close to the value(567.4 cm−1) reported in large-area freestanding GaN films [9].Meanwhile, the E2 peak of GaN on the bulk Si substrate wasmeasured at 565.8 cm−1, indicating a tensile stress in the GaNfilm. The warpage of the GaN-on-SOI wafer is ∼ 100 μm (incomparison with ∼ 45 μm in the GaN-on-Si wafer) because ofthe residual stress of the 5-μm-thick (111) Si device layer andthe fact that the GaN buffer/transition layers were optimizedfor the Si bulk substrate. The GaN epilayers will be furtheroptimized for the SOI substrate in future work. Table I showsthe basic characteristics of the SOI and bulk Si samples.

The device fabrication commenced with mesa isolation byCl2/He dry etching. Then, the source/drain ohmic metal stackTi/Al/Ni/Au was deposited by electron-beam evaporation, fol-lowed by rapid thermal annealing in an N2 ambient at 850 ◦Cfor 35 s. Gate metal Ni/Au was then deposited, followed witha 400 ◦C post-gate annealing in an N2 ambient for 10 min.Devices with and without AlN/Al2O3 (2 nm/10 nm) dielectricpassivation [10] were fabricated. For the E-mode devices, CF4

plasma treatment was applied prior to gate metal deposition[11]. D-mode and E-mode HEMTs were fabricated on the samesample, as shown in Fig. 1(c). In this letter, the gate length LG

of all the devices is 1.5 μm, and the gate-to-source distance LGS

is also 1.5 μm. The gate-to-drain distance LGD is designed tobe 5, 10, 15, and 20 μm.

III. RESULTS AND DISCUSSION

The dc output and transfer characteristics of D-mode andE-mode HEMTs on the GaN-on-SOI wafer were plotted inFig. 2. All the devices presented here feature a LG of 1.5 μmand a gate width WG of 10 μm. The threshold voltage is −4.0 Vfor the D-mode device and +0.9 V for the E-mode device atVDS = 10 V. The subthreshold slope is ∼75 mV/dec in both

Fig. 3. Three-terminal OFF-state characteristic of the E-mode HEMTs onGaN-on-SOI wafer at VGS = 0 V. (a) Unpassivated device and (b) passivateddevice with a floating termination at the Si handle wafer. (c) Unpassivateddevice and (d) passivated device with a ground termination at the Si handlewafer.

the D-mode and E-mode devices. The peak transconductanceGm of the D-mode and E-mode devices is ∼150 mS/mm. Themaximum drain current is 646 and 315 mA/mm in the D-mode(at VGS = 1 V) and E-mode (at VGS = 2.5 V) HEMTs, re-spectively. It has been confirmed that the GaN-on-SOI waferand the GaN-on-Si (bulk) wafer present a similar self-heatingeffect (with a 10 W/mm power density). This is because the4-μm GaN epilayer and the 5-μm (111) Si above the oxide layeris able to spread the heat from the hot spot, unlike the inefficientheat dissipation in Si SOI CMOS wafers with thin Si (at mostseveral hundred nanometers thick) above the oxide [12].

Using the method described in [10], dynamic ON-resistancewas measured to be 1.57 times of the static value on thepassivated E-mode HEMT (LGD = 10 μm) with a 100-msswitching time and 200-V OFF-state stress. It is noted that the100-ms switching time only allows evaluation of “slow trap”suppression at present and should be shortened with appropriatetesting equipment in the future.

The OFF-state characteristics are measured by an AgilentB1505 power device analyzer/curve tracer. Fig. 3(b) and (c)shows the three-terminal OFF-state breakdown characteristicsin passivated and unpassivated E-mode HEMTs with LGD =20 μm fabricated on the GaN-on-SOI wafer. For the passivateddevice, the OFF-state leakage current measured below 800-Vdrain bias is increased by about one order of magnitude com-pared with the unpassivated E-mode HEMT, as a result ofthe lateral leakage current through the AlN/Al2O3 passivationlayer. A drain leakage criterion of Id = 10 μA/mm is used asthe breakdown criterion. For E-mode devices with the substratefloating (by setting the chuck of the probe station floating),the breakdown is dominated by gate leakage and is measuredto be 1354 V for the passivated device and 1471 V for theunpassivated device. When the substrate is grounded throughthe chuck of the probe station, the breakdown voltage is 806 Vfor the passivated device and 832 V for the unpassivated device.The vertical substrate-to-drain leakage path starts to dominate

JIANG et al.: 1.4-kV AlGaN/GaN HEMTs ON A GaN-ON-SOI PLATFORM 359

Fig. 4. Vertical leakage characteristics on the GaN-on-SOI and GaN-on-Si(bulk) platforms. Multiple points are measured on different dies across thesamples. (Inset) Two-terminal test configuration.

Fig. 5. RON versus breakdown voltage for the E-mode HEMTs fabricatedon the GaN-on-SOI platform. Source/drain ohmic contacts (with an extensionlength of 1.5 μm for each contact) were included in the calculation of RON.

the drain leakage current at VDS > 500 V and eventually leadsto the drain “breakdown” that is defined by a leakage currentcriterion [13].

To investigate the effects of the SiO2 layer of the SOIwafer on the vertical leakage current, two-terminal I–V char-acteristics were measured between isolated ohmic contact pads(100 μm × 100 μm) on top and the handle wafer at the bottom,as shown in Fig. 4. Asymmetric characteristics were observed.At forward bias (with the top electrode positively biased), theSiO2 layer delays the onset of the sharp rise by 95 V (i.e.,VP2 − VP1), which is approximately the breakdown voltage ofthe 0.2-μm SiO2 layer. This sharp rise of the leakage currentat larger bias corresponds to the electrons’ injection from theSi over the barrier at the III-nitride/Si interface, after which theleakage is dominated by space-charge-limited current conduc-tion through the GaN buffer/transition layers [13]. At reversebias (with the top electrode negatively biased), the GaN-on-SOI sample clearly exhibits the smaller leakage current before−600 V as the SiO2 layer provides an energy barrier that blocksthe electrons’ conduction downward to the handle wafer. Thevertical leakage characteristics are reproducible across both theGaN-on-SOI and GaN-on-Si (bulk) samples, as suggested fromthe multiple-point testing results in Fig. 4.

The relationship between the specific ON-resistance andthe breakdown voltage for the E-mode HEMTs (with LGD =5, 10, 15, 20 μm) was plotted in Fig. 5, suggesting that thedevices on the SOI platform are competitive with the state-of-the-art devices on the bulk Si substrate [14]–[16]. The major

benefit of the GaN-on-SOI platform is the dual Si orientationsin the Si device layer and Si handle wafer.

IV. CONCLUSION

High-voltage D-mode and E-mode AlGaN/GaN HEMTs fab-ricated on GaN-on-SOI platform have been demonstrated. Thedevices feature high breakdown voltage, low ON-resistance,and reduced vertical leakage on a GaN-on-SOI platform. TheSOI wafer provides the flexibility of using different crystalline-orientation Si for various applications.

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